PWM Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 5.000s 530.120us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 7.000s 103.354us 5 5 100.00
V1 csr_rw pwm_csr_rw 8.000s 14.081us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 9.000s 1.048ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 9.000s 1.673ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 7.000s 18.180us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 8.000s 14.081us 20 20 100.00
pwm_csr_aliasing 9.000s 1.673ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.400m 10.942ms 50 50 100.00
V2 pulse pwm_rand_output 1.400m 10.942ms 50 50 100.00
V2 blink pwm_rand_output 1.400m 10.942ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.400m 10.942ms 50 50 100.00
V2 resolution pwm_rand_output 1.400m 10.942ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.400m 10.942ms 50 50 100.00
V2 polarity pwm_rand_output 1.400m 10.942ms 50 50 100.00
V2 phase pwm_rand_output 1.400m 10.942ms 50 50 100.00
V2 lowpower pwm_rand_output 1.400m 10.942ms 50 50 100.00
V2 perf pwm_perf 51.000s 43.757ms 50 50 100.00
V2 stress_all pwm_stress_all 8.533m 66.156ms 49 50 98.00
V2 alert_test pwm_alert_test 3.000s 156.053us 50 50 100.00
V2 intr_test pwm_intr_test 7.000s 45.107us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 195.272us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 195.272us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 7.000s 103.354us 5 5 100.00
pwm_csr_rw 8.000s 14.081us 20 20 100.00
pwm_csr_aliasing 9.000s 1.673ms 5 5 100.00
pwm_same_csr_outstanding 7.000s 68.710us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 7.000s 103.354us 5 5 100.00
pwm_csr_rw 8.000s 14.081us 20 20 100.00
pwm_csr_aliasing 9.000s 1.673ms 5 5 100.00
pwm_same_csr_outstanding 7.000s 68.710us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 9.000s 107.039us 20 20 100.00
pwm_sec_cm 3.000s 141.173us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 9.000s 107.039us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.73 99.69 99.45 99.96 95.61 94.92 -- 100.00 99.01

Failure Buckets

Past Results