PWM Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 6.000s 1.062ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 45.748us 5 5 100.00
V1 csr_rw pwm_csr_rw 7.000s 17.022us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 12.000s 2.554ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 100.405us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 4.000s 105.728us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 7.000s 17.022us 20 20 100.00
pwm_csr_aliasing 5.000s 100.405us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 3.567m 45.646ms 50 50 100.00
V2 pulse pwm_rand_output 3.567m 45.646ms 50 50 100.00
V2 blink pwm_rand_output 3.567m 45.646ms 50 50 100.00
V2 heartbeat pwm_rand_output 3.567m 45.646ms 50 50 100.00
V2 resolution pwm_rand_output 3.567m 45.646ms 50 50 100.00
V2 multi_channel pwm_rand_output 3.567m 45.646ms 50 50 100.00
V2 polarity pwm_rand_output 3.567m 45.646ms 50 50 100.00
V2 phase pwm_rand_output 3.567m 45.646ms 50 50 100.00
V2 lowpower pwm_rand_output 3.567m 45.646ms 50 50 100.00
V2 perf pwm_perf 50.000s 41.992ms 50 50 100.00
V2 stress_all pwm_stress_all 4.650m 244.264ms 49 50 98.00
V2 alert_test pwm_alert_test 4.000s 15.933us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 18.189us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 7.000s 77.855us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 7.000s 77.855us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 45.748us 5 5 100.00
pwm_csr_rw 7.000s 17.022us 20 20 100.00
pwm_csr_aliasing 5.000s 100.405us 5 5 100.00
pwm_same_csr_outstanding 4.000s 213.755us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 45.748us 5 5 100.00
pwm_csr_rw 7.000s 17.022us 20 20 100.00
pwm_csr_aliasing 5.000s 100.405us 5 5 100.00
pwm_same_csr_outstanding 4.000s 213.755us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 6.000s 126.523us 20 20 100.00
pwm_sec_cm 3.000s 523.983us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 6.000s 126.523us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.41 99.34 98.83 99.88 94.93 94.92 -- 100.00 99.01

Failure Buckets

Past Results