a8c9c17a8c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 14.000s | 3.172ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 9.000s | 45.777us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 7.000s | 47.747us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 20.000s | 952.571us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 8.000s | 23.528us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 8.000s | 28.657us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 7.000s | 47.747us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 8.000s | 23.528us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.433m | 43.753ms | 48 | 50 | 96.00 |
| V2 | pulse | pwm_rand_output | 1.433m | 43.753ms | 48 | 50 | 96.00 |
| V2 | blink | pwm_rand_output | 1.433m | 43.753ms | 48 | 50 | 96.00 |
| V2 | heartbeat | pwm_rand_output | 1.433m | 43.753ms | 48 | 50 | 96.00 |
| V2 | resolution | pwm_rand_output | 1.433m | 43.753ms | 48 | 50 | 96.00 |
| V2 | multi_channel | pwm_rand_output | 1.433m | 43.753ms | 48 | 50 | 96.00 |
| V2 | polarity | pwm_rand_output | 1.433m | 43.753ms | 48 | 50 | 96.00 |
| V2 | phase | pwm_rand_output | 1.433m | 43.753ms | 48 | 50 | 96.00 |
| V2 | lowpower | pwm_rand_output | 1.433m | 43.753ms | 48 | 50 | 96.00 |
| V2 | perf | pwm_perf | 1.033m | 10.720ms | 50 | 50 | 100.00 |
| V2 | stress_all | pwm_stress_all | 4.567m | 65.312ms | 49 | 50 | 98.00 |
| V2 | alert_test | pwm_alert_test | 12.000s | 14.686us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 8.000s | 14.805us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 10.000s | 44.025us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 10.000s | 44.025us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 9.000s | 45.777us | 5 | 5 | 100.00 |
| pwm_csr_rw | 7.000s | 47.747us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 8.000s | 23.528us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 9.000s | 578.459us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 9.000s | 45.777us | 5 | 5 | 100.00 |
| pwm_csr_rw | 7.000s | 47.747us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 8.000s | 23.528us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 9.000s | 578.459us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 17.000s | 685.719us | 20 | 20 | 100.00 |
| pwm_sec_cm | 7.000s | 133.859us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 17.000s | 685.719us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 417 | 420 | 99.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.23 | 99.17 | 98.52 | 99.84 | 94.52 | 94.92 | -- | 100.00 | 99.01 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
13.pwm_rand_output.13347004783279997847208196064709777204982916296261138291345091292199809728088
Line 351, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/13.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.pwm_rand_output.74658524313633991974711888235316801577371256487311754978122308383555326323280
Line 354, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/32.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:
8.pwm_stress_all.10452380142815110282884807874180351865125450057494946102360320603078970677840
Line 33485, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/8.pwm_stress_all/latest/run.log
UVM_ERROR @ 139759422383 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 139759422383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---