PWM Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	1.414ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	16.082us	5	5	100.00
V1	csr_rw	pwm_csr_rw	7.000s	21.231us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	571.948us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	147.826us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	13.000s	368.133us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	7.000s	21.231us	20	20	100.00
		pwm_csr_aliasing	4.000s	147.826us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.750m	21.431ms	50	50	100.00
V2	pulse	pwm_rand_output	1.750m	21.431ms	50	50	100.00
V2	blink	pwm_rand_output	1.750m	21.431ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.750m	21.431ms	50	50	100.00
V2	resolution	pwm_rand_output	1.750m	21.431ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.750m	21.431ms	50	50	100.00
V2	polarity	pwm_rand_output	1.750m	21.431ms	50	50	100.00
V2	phase	pwm_rand_output	1.750m	21.431ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.750m	21.431ms	50	50	100.00
V2	perf	pwm_perf	52.000s	21.875ms	50	50	100.00
V2	stress_all	pwm_stress_all	5.583m	65.318ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	33.027us	50	50	100.00
V2	intr_test	pwm_intr_test	7.000s	20.749us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	8.000s	41.467us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	8.000s	41.467us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	16.082us	5	5	100.00
		pwm_csr_rw	7.000s	21.231us	20	20	100.00
		pwm_csr_aliasing	4.000s	147.826us	5	5	100.00
		pwm_same_csr_outstanding	9.000s	33.888us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	16.082us	5	5	100.00
		pwm_csr_rw	7.000s	21.231us	20	20	100.00
		pwm_csr_aliasing	4.000s	147.826us	5	5	100.00
		pwm_same_csr_outstanding	9.000s	33.888us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	8.000s	71.434us	20	20	100.00
		pwm_sec_cm	4.000s	365.019us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	8.000s	71.434us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.47	99.48	99.08	99.88	94.93	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

26.pwm_stress_all.77993345876124667947924909037742405258520914663017252613000863937188187169256
Line 425749, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/26.pwm_stress_all/latest/run.log

  UVM_ERROR @ 14492557667 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [2] did not MATCH
  UVM_INFO @ 14492557667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.pwm_stress_all.62477588479570410637006223961925786207228037220687667914997477003286510976192
Line 539726, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/40.pwm_stress_all/latest/run.log

  UVM_ERROR @ 46851106410 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 46851106410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---