PWM Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: `548a3880d8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	10.000s	517.023us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	16.736us	5	5	100.00
V1	csr_rw	pwm_csr_rw	4.000s	24.724us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	8.000s	289.938us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	91.667us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	124.797us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	4.000s	24.724us	20	20	100.00
		pwm_csr_aliasing	4.000s	91.667us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.850m	22.344ms	50	50	100.00
V2	pulse	pwm_rand_output	1.850m	22.344ms	50	50	100.00
V2	blink	pwm_rand_output	1.850m	22.344ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.850m	22.344ms	50	50	100.00
V2	resolution	pwm_rand_output	1.850m	22.344ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.850m	22.344ms	50	50	100.00
V2	polarity	pwm_rand_output	1.850m	22.344ms	50	50	100.00
V2	phase	pwm_rand_output	1.850m	22.344ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.850m	22.344ms	50	50	100.00
V2	perf	pwm_perf	54.000s	41.996ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.583m	132.310ms	48	50	96.00
V2	alert_test	pwm_alert_test	7.000s	45.565us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	20.279us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	157.246us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	157.246us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	16.736us	5	5	100.00
		pwm_csr_rw	4.000s	24.724us	20	20	100.00
		pwm_csr_aliasing	4.000s	91.667us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	57.479us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	16.736us	5	5	100.00
		pwm_csr_rw	4.000s	24.724us	20	20	100.00
		pwm_csr_aliasing	4.000s	91.667us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	57.479us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	4.000s	119.479us	20	20	100.00
		pwm_sec_cm	3.000s	260.539us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	4.000s	119.479us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.53	99.55	99.20	99.92	95.00	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

21.pwm_stress_all.115631054333613649420710621448878181737557402115932635799946179700198419433177
Line 787172, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/21.pwm_stress_all/latest/run.log

  UVM_ERROR @ 21837910802 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 21837910802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.pwm_stress_all.76214273841148357911803311123787225959651699474761975669315481935342126478453
Line 3596792, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/33.pwm_stress_all/latest/run.log

  UVM_ERROR @ 44092565513 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [1] did not MATCH
  UVM_INFO @ 44092565513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---