6e698b4dfe
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 5.000s | 656.601us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 120.282us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 3.000s | 61.787us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 1.351ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 289.976us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 3.000s | 38.889us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 61.787us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 4.000s | 289.976us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 2.017m | 10.609ms | 50 | 50 | 100.00 |
V2 | pulse | pwm_rand_output | 2.017m | 10.609ms | 50 | 50 | 100.00 |
V2 | blink | pwm_rand_output | 2.017m | 10.609ms | 50 | 50 | 100.00 |
V2 | heartbeat | pwm_rand_output | 2.017m | 10.609ms | 50 | 50 | 100.00 |
V2 | resolution | pwm_rand_output | 2.017m | 10.609ms | 50 | 50 | 100.00 |
V2 | multi_channel | pwm_rand_output | 2.017m | 10.609ms | 50 | 50 | 100.00 |
V2 | polarity | pwm_rand_output | 2.017m | 10.609ms | 50 | 50 | 100.00 |
V2 | phase | pwm_rand_output | 2.017m | 10.609ms | 50 | 50 | 100.00 |
V2 | lowpower | pwm_rand_output | 2.017m | 10.609ms | 50 | 50 | 100.00 |
V2 | perf | pwm_perf | 50.000s | 42.003ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 3.900m | 194.458ms | 47 | 50 | 94.00 |
V2 | alert_test | pwm_alert_test | 3.000s | 14.668us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 3.000s | 12.204us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 46.202us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 46.202us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 120.282us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 61.787us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 4.000s | 289.976us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 158.618us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 120.282us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 61.787us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 4.000s | 289.976us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 158.618us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 287 | 290 | 98.97 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 4.000s | 479.893us | 20 | 20 | 100.00 |
pwm_sec_cm | 3.000s | 45.533us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 4.000s | 479.893us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 417 | 420 | 99.29 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 6 | 85.71 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.57 | 99.59 | 99.26 | 99.96 | 95.07 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 3 failures:
26.pwm_stress_all.62648107296361313359658471501577391595206404847130853316772672546608964765589
Line 932, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/26.pwm_stress_all/latest/run.log
UVM_ERROR @ 561252752411 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 561252752411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.pwm_stress_all.14588188428734316772915006181190962490094565913029038399710360378422347704395
Line 1876132, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/36.pwm_stress_all/latest/run.log
UVM_ERROR @ 89876963204 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 89876963204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.