PWM Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	11.000s	517.223us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	9.000s	76.521us	5	5	100.00
V1	csr_rw	pwm_csr_rw	17.000s	17.583us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	667.610us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	7.000s	79.692us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	8.000s	25.283us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	17.000s	17.583us	20	20	100.00
		pwm_csr_aliasing	7.000s	79.692us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.117m	21.000ms	50	50	100.00
V2	pulse	pwm_rand_output	2.117m	21.000ms	50	50	100.00
V2	blink	pwm_rand_output	2.117m	21.000ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.117m	21.000ms	50	50	100.00
V2	resolution	pwm_rand_output	2.117m	21.000ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.117m	21.000ms	50	50	100.00
V2	polarity	pwm_rand_output	2.117m	21.000ms	50	50	100.00
V2	phase	pwm_rand_output	2.117m	21.000ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.117m	21.000ms	50	50	100.00
V2	perf	pwm_perf	58.000s	10.716ms	50	50	100.00
V2	stress_all	pwm_stress_all	5.033m	128.027ms	48	50	96.00
V2	alert_test	pwm_alert_test	12.000s	24.905us	50	50	100.00
V2	intr_test	pwm_intr_test	22.000s	16.510us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	23.000s	30.627us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	23.000s	30.627us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	9.000s	76.521us	5	5	100.00
		pwm_csr_rw	17.000s	17.583us	20	20	100.00
		pwm_csr_aliasing	7.000s	79.692us	5	5	100.00
		pwm_same_csr_outstanding	9.000s	123.293us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	9.000s	76.521us	5	5	100.00
		pwm_csr_rw	17.000s	17.583us	20	20	100.00
		pwm_csr_aliasing	7.000s	79.692us	5	5	100.00
		pwm_same_csr_outstanding	9.000s	123.293us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	9.000s	698.970us	20	20	100.00
		pwm_sec_cm	9.000s	35.993us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	9.000s	698.970us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.55	99.59	99.26	99.88	95.10	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

2.pwm_stress_all.97763033390670979289112716540073836194025308740636666148617227767320404333849
Line 5023497, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/2.pwm_stress_all/latest/run.log

  UVM_ERROR @ 51917935506 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [1] did not MATCH
  UVM_INFO @ 51917935506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.pwm_stress_all.66364174326466179348342722812015167097935089402471869976121841130098222959272
Line 3554, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/49.pwm_stress_all/latest/run.log

  UVM_ERROR @ 21946086821 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 21946086821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---