PWM Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 6.000s 1.024ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 29.070us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 41.283us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 676.579us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 82.489us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 3.000s 39.469us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 41.283us 20 20 100.00
pwm_csr_aliasing 4.000s 82.489us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.500m 10.944ms 50 50 100.00
V2 pulse pwm_rand_output 1.500m 10.944ms 50 50 100.00
V2 blink pwm_rand_output 1.500m 10.944ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.500m 10.944ms 50 50 100.00
V2 resolution pwm_rand_output 1.500m 10.944ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.500m 10.944ms 50 50 100.00
V2 polarity pwm_rand_output 1.500m 10.944ms 50 50 100.00
V2 phase pwm_rand_output 1.500m 10.944ms 50 50 100.00
V2 lowpower pwm_rand_output 1.500m 10.944ms 50 50 100.00
V2 perf pwm_perf 52.000s 27.636ms 49 50 98.00
V2 stress_all pwm_stress_all 4.000m 264.608ms 49 50 98.00
V2 alert_test pwm_alert_test 3.000s 22.788us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 14.291us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 321.275us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 321.275us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 29.070us 5 5 100.00
pwm_csr_rw 3.000s 41.283us 20 20 100.00
pwm_csr_aliasing 4.000s 82.489us 5 5 100.00
pwm_same_csr_outstanding 4.000s 112.704us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 29.070us 5 5 100.00
pwm_csr_rw 3.000s 41.283us 20 20 100.00
pwm_csr_aliasing 4.000s 82.489us 5 5 100.00
pwm_same_csr_outstanding 4.000s 112.704us 20 20 100.00
V2 TOTAL 288 290 99.31
V2S tl_intg_err pwm_tl_intg_err 5.000s 1.257ms 20 20 100.00
pwm_sec_cm 3.000s 34.638us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 1.257ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 418 420 99.52

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 5 71.43
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.44 99.48 99.08 99.84 94.86 94.92 -- 100.00 99.01

Failure Buckets

Past Results