8db2a18db1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 14.000s | 511.895us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 15.963us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 148.618us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 937.518us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 34.787us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 3.000s | 174.213us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 148.618us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 34.787us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.400m | 11.670ms | 50 | 50 | 100.00 |
| V2 | pulse | pwm_rand_output | 1.400m | 11.670ms | 50 | 50 | 100.00 |
| V2 | blink | pwm_rand_output | 1.400m | 11.670ms | 50 | 50 | 100.00 |
| V2 | heartbeat | pwm_rand_output | 1.400m | 11.670ms | 50 | 50 | 100.00 |
| V2 | resolution | pwm_rand_output | 1.400m | 11.670ms | 50 | 50 | 100.00 |
| V2 | multi_channel | pwm_rand_output | 1.400m | 11.670ms | 50 | 50 | 100.00 |
| V2 | polarity | pwm_rand_output | 1.400m | 11.670ms | 50 | 50 | 100.00 |
| V2 | phase | pwm_rand_output | 1.400m | 11.670ms | 50 | 50 | 100.00 |
| V2 | lowpower | pwm_rand_output | 1.400m | 11.670ms | 50 | 50 | 100.00 |
| V2 | perf | pwm_perf | 50.000s | 43.748ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 4.700m | 66.855ms | 49 | 50 | 98.00 |
| V2 | alert_test | pwm_alert_test | 7.000s | 24.168us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 12.381us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 47.461us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 47.461us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 15.963us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 148.618us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 34.787us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 274.948us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 15.963us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 148.618us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 34.787us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 274.948us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 504.045us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 43.315us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 504.045us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 418 | 420 | 99.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.51 | 99.48 | 99.08 | 99.92 | 95.03 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:
2.pwm_stress_all.248266404038316582345579924610645826320505090987464786063464790070984066491
Line 164492, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/2.pwm_stress_all/latest/run.log
UVM_ERROR @ 21769702858 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 21769702858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
8.pwm_perf.102757327965955734037159397926799711296330661132168613963008798269042466101229
Line 399, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/8.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---