3d5220a43f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 5.000s | 516.995us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 43.626us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 93.076us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 2.745ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 427.990us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 80.713us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 93.076us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 427.990us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 2.350m | 43.749ms | 50 | 50 | 100.00 |
| V2 | pulse | pwm_rand_output | 2.350m | 43.749ms | 50 | 50 | 100.00 |
| V2 | blink | pwm_rand_output | 2.350m | 43.749ms | 50 | 50 | 100.00 |
| V2 | heartbeat | pwm_rand_output | 2.350m | 43.749ms | 50 | 50 | 100.00 |
| V2 | resolution | pwm_rand_output | 2.350m | 43.749ms | 50 | 50 | 100.00 |
| V2 | multi_channel | pwm_rand_output | 2.350m | 43.749ms | 50 | 50 | 100.00 |
| V2 | polarity | pwm_rand_output | 2.350m | 43.749ms | 50 | 50 | 100.00 |
| V2 | phase | pwm_rand_output | 2.350m | 43.749ms | 50 | 50 | 100.00 |
| V2 | lowpower | pwm_rand_output | 2.350m | 43.749ms | 50 | 50 | 100.00 |
| V2 | perf | pwm_perf | 51.000s | 22.346ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 5.550m | 64.799ms | 49 | 50 | 98.00 |
| V2 | alert_test | pwm_alert_test | 3.000s | 26.866us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 16.515us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 456.414us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 456.414us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 43.626us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 93.076us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 427.990us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 95.699us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 43.626us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 93.076us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 427.990us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 95.699us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 305.293us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 96.577us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 305.293us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 418 | 420 | 99.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.62 | 99.62 | 99.32 | 99.96 | 95.20 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:
42.pwm_stress_all.72210546600449916746459608784450745282799403979996746349248078018123646901825
Line 826, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/42.pwm_stress_all/latest/run.log
UVM_ERROR @ 33349001160 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [2] did not MATCH
UVM_INFO @ 33349001160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
43.pwm_perf.19658756283398055866997430883740462456023577523279656496807358223201211033986
Line 379, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/43.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---