b33f0bcb4a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 5.000s | 2.034ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 20.956us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 61.869us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 1.380ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 306.987us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 3.000s | 23.317us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 61.869us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 306.987us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.067m | 10.504ms | 49 | 50 | 98.00 |
| V2 | pulse | pwm_rand_output | 1.067m | 10.504ms | 49 | 50 | 98.00 |
| V2 | blink | pwm_rand_output | 1.067m | 10.504ms | 49 | 50 | 98.00 |
| V2 | heartbeat | pwm_rand_output | 1.067m | 10.504ms | 49 | 50 | 98.00 |
| V2 | resolution | pwm_rand_output | 1.067m | 10.504ms | 49 | 50 | 98.00 |
| V2 | multi_channel | pwm_rand_output | 1.067m | 10.504ms | 49 | 50 | 98.00 |
| V2 | polarity | pwm_rand_output | 1.067m | 10.504ms | 49 | 50 | 98.00 |
| V2 | phase | pwm_rand_output | 1.067m | 10.504ms | 49 | 50 | 98.00 |
| V2 | lowpower | pwm_rand_output | 1.067m | 10.504ms | 49 | 50 | 98.00 |
| V2 | perf | pwm_perf | 49.000s | 17.505ms | 50 | 50 | 100.00 |
| V2 | stress_all | pwm_stress_all | 5.067m | 64.944ms | 47 | 50 | 94.00 |
| V2 | alert_test | pwm_alert_test | 3.000s | 125.649us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 13.891us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 209.639us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 209.639us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 20.956us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 61.869us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 306.987us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 103.133us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 20.956us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 61.869us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 306.987us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 103.133us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 4.000s | 96.942us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 245.080us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 4.000s | 96.942us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 416 | 420 | 99.05 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.17 | 99.14 | 98.46 | 99.72 | 94.48 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:
36.pwm_stress_all.34419765667890155572678072934129638039542394970637099939662330041009062720286
Line 146552, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/36.pwm_stress_all/latest/run.log
UVM_ERROR @ 17547934271 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 17547934271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.pwm_stress_all.14521039336907422232384894462111250943226341077833670986569405017428529890241
Line 8880, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/39.pwm_stress_all/latest/run.log
UVM_ERROR @ 91281127348 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 91281127348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
4.pwm_rand_output.99151525811406307281337909429184033102134509477300045035123414054724211956462
Line 400, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/4.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---