PWM Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: `abd7ce57f2`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	535.377us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	19.422us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	62.590us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	473.924us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	3.000s	99.888us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	3.000s	39.305us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	62.590us	20	20	100.00
		pwm_csr_aliasing	3.000s	99.888us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.000m	200.000ms	49	50	98.00
V2	pulse	pwm_rand_output	1.000m	200.000ms	49	50	98.00
V2	blink	pwm_rand_output	1.000m	200.000ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.000m	200.000ms	49	50	98.00
V2	resolution	pwm_rand_output	1.000m	200.000ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.000m	200.000ms	49	50	98.00
V2	polarity	pwm_rand_output	1.000m	200.000ms	49	50	98.00
V2	phase	pwm_rand_output	1.000m	200.000ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.000m	200.000ms	49	50	98.00
V2	perf	pwm_perf	50.000s	10.506ms	49	50	98.00
V2	stress_all	pwm_stress_all	4.150m	63.640ms	46	50	92.00
V2	alert_test	pwm_alert_test	3.000s	40.429us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	94.503us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	5.000s	107.710us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	5.000s	107.710us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	19.422us	5	5	100.00
		pwm_csr_rw	3.000s	62.590us	20	20	100.00
		pwm_csr_aliasing	3.000s	99.888us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	34.537us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	19.422us	5	5	100.00
		pwm_csr_rw	3.000s	62.590us	20	20	100.00
		pwm_csr_aliasing	3.000s	99.888us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	34.537us	20	20	100.00
V2		TOTAL			284	290	97.93
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	224.436us	20	20	100.00
		pwm_sec_cm	3.000s	58.729us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	224.436us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			414	420	98.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.56	99.59	99.26	99.88	95.17	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 4 failures:

Test pwm_stress_all has 4 failures.

3.pwm_stress_all.77425289254694998829354981989146498993551460637717486548881520723926441447771
Line 457, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/3.pwm_stress_all/latest/run.log

  UVM_ERROR @ 43767579556 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [4] did not MATCH
  UVM_INFO @ 43767579556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.pwm_stress_all.82172514211014528512874315255883403927156400995162900514704015396966168128852
Line 115299, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/4.pwm_stress_all/latest/run.log

  UVM_ERROR @ 168478540743 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 168478540743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test pwm_perf has 1 failures.
  - 36.pwm_perf.34448009732077074128921905471591681263159620292039412146531043393769548522218
    Line 325, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/36.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwm_rand_output has 1 failures.
  - 49.pwm_rand_output.76019419282232907497131818022968445863909111141154932575393881108509672806871
    Line 1142929, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/49.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```