PWM Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 5.000s 514.370us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 44.784us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 14.996us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 6.384ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 700.721us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 4.000s 60.732us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 14.996us 20 20 100.00
pwm_csr_aliasing 4.000s 700.721us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.633m 200.000ms 48 50 96.00
V2 pulse pwm_rand_output 1.633m 200.000ms 48 50 96.00
V2 blink pwm_rand_output 1.633m 200.000ms 48 50 96.00
V2 heartbeat pwm_rand_output 1.633m 200.000ms 48 50 96.00
V2 resolution pwm_rand_output 1.633m 200.000ms 48 50 96.00
V2 multi_channel pwm_rand_output 1.633m 200.000ms 48 50 96.00
V2 polarity pwm_rand_output 1.633m 200.000ms 48 50 96.00
V2 phase pwm_rand_output 1.633m 200.000ms 48 50 96.00
V2 lowpower pwm_rand_output 1.633m 200.000ms 48 50 96.00
V2 perf pwm_perf 51.000s 43.741ms 48 50 96.00
V2 stress_all pwm_stress_all 4.967m 306.229ms 48 50 96.00
V2 alert_test pwm_alert_test 7.000s 23.930us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 21.347us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 154.302us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 154.302us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 44.784us 5 5 100.00
pwm_csr_rw 3.000s 14.996us 20 20 100.00
pwm_csr_aliasing 4.000s 700.721us 5 5 100.00
pwm_same_csr_outstanding 4.000s 40.934us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 44.784us 5 5 100.00
pwm_csr_rw 3.000s 14.996us 20 20 100.00
pwm_csr_aliasing 4.000s 700.721us 5 5 100.00
pwm_same_csr_outstanding 4.000s 40.934us 20 20 100.00
V2 TOTAL 284 290 97.93
V2S tl_intg_err pwm_tl_intg_err 5.000s 2.085ms 20 20 100.00
pwm_sec_cm 7.000s 245.249us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 2.085ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 414 420 98.57

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 4 57.14
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.30 99.38 98.89 99.80 94.48 94.92 -- 100.00 99.01

Failure Buckets

Past Results