PWM Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	514.370us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	44.784us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	14.996us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	6.384ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	700.721us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	60.732us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	14.996us	20	20	100.00
		pwm_csr_aliasing	4.000s	700.721us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.633m	200.000ms	48	50	96.00
V2	pulse	pwm_rand_output	1.633m	200.000ms	48	50	96.00
V2	blink	pwm_rand_output	1.633m	200.000ms	48	50	96.00
V2	heartbeat	pwm_rand_output	1.633m	200.000ms	48	50	96.00
V2	resolution	pwm_rand_output	1.633m	200.000ms	48	50	96.00
V2	multi_channel	pwm_rand_output	1.633m	200.000ms	48	50	96.00
V2	polarity	pwm_rand_output	1.633m	200.000ms	48	50	96.00
V2	phase	pwm_rand_output	1.633m	200.000ms	48	50	96.00
V2	lowpower	pwm_rand_output	1.633m	200.000ms	48	50	96.00
V2	perf	pwm_perf	51.000s	43.741ms	48	50	96.00
V2	stress_all	pwm_stress_all	4.967m	306.229ms	48	50	96.00
V2	alert_test	pwm_alert_test	7.000s	23.930us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	21.347us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	154.302us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	154.302us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	44.784us	5	5	100.00
		pwm_csr_rw	3.000s	14.996us	20	20	100.00
		pwm_csr_aliasing	4.000s	700.721us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	40.934us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	44.784us	5	5	100.00
		pwm_csr_rw	3.000s	14.996us	20	20	100.00
		pwm_csr_aliasing	4.000s	700.721us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	40.934us	20	20	100.00
V2		TOTAL			284	290	97.93
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	2.085ms	20	20	100.00
		pwm_sec_cm	7.000s	245.249us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	2.085ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			414	420	98.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.30	99.38	98.89	99.80	94.48	94.92	--	100.00	99.01

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

Test pwm_rand_output has 2 failures.

9.pwm_rand_output.27612105094358050673061153389930972337873160476611153383329343937870623320541
Line 7998337, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/9.pwm_rand_output/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.pwm_rand_output.71966808499611683970708352413314553725351553676093523867388726617243729622321
Line 403, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/40.pwm_rand_output/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwm_perf has 2 failures.

21.pwm_perf.1009783208287233903235371688114098920713678711374783423068741200871847041360
Line 349, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/21.pwm_perf/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.pwm_perf.40494279747950523896026447284826984834526133635381366241029857654390306257151
Line 349, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/38.pwm_perf/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

8.pwm_stress_all.25687064695147997188167632341831992598238200053583603822651294291385046941750
Line 613, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/8.pwm_stress_all/latest/run.log

  UVM_ERROR @ 15610197614 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [1] did not MATCH
  UVM_INFO @ 15610197614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.pwm_stress_all.32321141065189741421223869207525011753380404734533289844814035129219998884523
Line 6902, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/22.pwm_stress_all/latest/run.log

  UVM_ERROR @ 65855530401 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 65855530401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---