3e678c112b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 5.000s | 513.306us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 35.121us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 13.982us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 12.000s | 790.816us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 100.469us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 8.000s | 62.875us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 13.982us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 5.000s | 100.469us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.133m | 10.718ms | 50 | 50 | 100.00 |
| V2 | pulse | pwm_rand_output | 1.133m | 10.718ms | 50 | 50 | 100.00 |
| V2 | blink | pwm_rand_output | 1.133m | 10.718ms | 50 | 50 | 100.00 |
| V2 | heartbeat | pwm_rand_output | 1.133m | 10.718ms | 50 | 50 | 100.00 |
| V2 | resolution | pwm_rand_output | 1.133m | 10.718ms | 50 | 50 | 100.00 |
| V2 | multi_channel | pwm_rand_output | 1.133m | 10.718ms | 50 | 50 | 100.00 |
| V2 | polarity | pwm_rand_output | 1.133m | 10.718ms | 50 | 50 | 100.00 |
| V2 | phase | pwm_rand_output | 1.133m | 10.718ms | 50 | 50 | 100.00 |
| V2 | lowpower | pwm_rand_output | 1.133m | 10.718ms | 50 | 50 | 100.00 |
| V2 | perf | pwm_perf | 51.000s | 43.753ms | 48 | 50 | 96.00 |
| V2 | stress_all | pwm_stress_all | 5.250m | 295.988ms | 46 | 50 | 92.00 |
| V2 | alert_test | pwm_alert_test | 3.000s | 15.460us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 7.000s | 21.056us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 10.000s | 47.489us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 10.000s | 47.489us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 35.121us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 13.982us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 100.469us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 8.000s | 149.564us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 35.121us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 13.982us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 100.469us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 8.000s | 149.564us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 284 | 290 | 97.93 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 8.000s | 725.223us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 45.097us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 8.000s | 725.223us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 414 | 420 | 98.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.57 | 99.55 | 99.20 | 99.88 | 95.27 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 4 failures:
6.pwm_stress_all.91800615343063863881086384785233177664457862191519714662517771451145421661981
Line 87880, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/6.pwm_stress_all/latest/run.log
UVM_ERROR @ 694548830 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 694548830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.pwm_stress_all.68430044688604097490357167657499925291792294190699778892954524197650243769963
Line 25279, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/9.pwm_stress_all/latest/run.log
UVM_ERROR @ 300018560983 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 300018560983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
5.pwm_perf.62223392718915943681824874185871968054835231982367305759335050582232063001243
Line 329, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/5.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.pwm_perf.59305277225233649584251333709135521967666070588859228409472001512150855271827
Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/10.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---