PWM Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 10.000s 1.218ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 7.000s 51.844us 5 5 100.00
V1 csr_rw pwm_csr_rw 7.000s 71.203us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 10.000s 1.905ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 91.487us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 8.000s 111.715us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 7.000s 71.203us 20 20 100.00
pwm_csr_aliasing 4.000s 91.487us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.533m 10.720ms 50 50 100.00
V2 pulse pwm_rand_output 1.533m 10.720ms 50 50 100.00
V2 blink pwm_rand_output 1.533m 10.720ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.533m 10.720ms 50 50 100.00
V2 resolution pwm_rand_output 1.533m 10.720ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.533m 10.720ms 50 50 100.00
V2 polarity pwm_rand_output 1.533m 10.720ms 50 50 100.00
V2 phase pwm_rand_output 1.533m 10.720ms 50 50 100.00
V2 lowpower pwm_rand_output 1.533m 10.720ms 50 50 100.00
V2 perf pwm_perf 53.000s 87.485ms 50 50 100.00
V2 stress_all pwm_stress_all 5.583m 86.039ms 47 50 94.00
V2 alert_test pwm_alert_test 4.000s 14.814us 50 50 100.00
V2 intr_test pwm_intr_test 12.000s 18.461us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 239.499us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 239.499us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 7.000s 51.844us 5 5 100.00
pwm_csr_rw 7.000s 71.203us 20 20 100.00
pwm_csr_aliasing 4.000s 91.487us 5 5 100.00
pwm_same_csr_outstanding 7.000s 35.781us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 7.000s 51.844us 5 5 100.00
pwm_csr_rw 7.000s 71.203us 20 20 100.00
pwm_csr_aliasing 4.000s 91.487us 5 5 100.00
pwm_same_csr_outstanding 7.000s 35.781us 20 20 100.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err pwm_tl_intg_err 9.000s 125.080us 20 20 100.00
pwm_sec_cm 3.000s 151.067us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 9.000s 125.080us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 417 420 99.29

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.71 99.69 99.45 99.96 95.51 94.92 -- 100.00 99.01

Failure Buckets

Past Results