PWM Simulation Results

Saturday July 06 2024 23:02:28 UTC

GitHub Revision: c42c47ec2d

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 3200059823452722292543998130245428086525417237473114929151723951411399280153

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 10.000s 2.119ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 61.220us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 40.338us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 10.000s 11.063ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 63.441us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 3.000s 39.012us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 40.338us 20 20 100.00
pwm_csr_aliasing 4.000s 63.441us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.233m 10.718ms 50 50 100.00
V2 pulse pwm_rand_output 1.233m 10.718ms 50 50 100.00
V2 blink pwm_rand_output 1.233m 10.718ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.233m 10.718ms 50 50 100.00
V2 resolution pwm_rand_output 1.233m 10.718ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.233m 10.718ms 50 50 100.00
V2 polarity pwm_rand_output 1.233m 10.718ms 50 50 100.00
V2 phase pwm_rand_output 1.233m 10.718ms 50 50 100.00
V2 lowpower pwm_rand_output 1.233m 10.718ms 50 50 100.00
V2 perf pwm_perf 50.000s 10.501ms 50 50 100.00
V2 stress_all pwm_stress_all 4.100m 63.499ms 47 50 94.00
V2 alert_test pwm_alert_test 7.000s 22.496us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 12.651us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 5.000s 43.873us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 5.000s 43.873us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 61.220us 5 5 100.00
pwm_csr_rw 3.000s 40.338us 20 20 100.00
pwm_csr_aliasing 4.000s 63.441us 5 5 100.00
pwm_same_csr_outstanding 7.000s 39.593us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 61.220us 5 5 100.00
pwm_csr_rw 3.000s 40.338us 20 20 100.00
pwm_csr_aliasing 4.000s 63.441us 5 5 100.00
pwm_same_csr_outstanding 7.000s 39.593us 20 20 100.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err pwm_tl_intg_err 4.000s 84.376us 20 20 100.00
pwm_sec_cm 3.000s 383.981us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 4.000s 84.376us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 417 420 99.29

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.29 99.24 98.65 99.88 94.59 94.92 -- 100.00 99.01

Failure Buckets

Past Results