2e5d86c9b5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 11.000s | 3.187ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 8.000s | 35.252us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 17.000s | 279.827us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 2.538ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 13.000s | 422.514us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 13.000s | 62.936us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 17.000s | 279.827us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 13.000s | 422.514us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 2.633m | 20.999ms | 49 | 50 | 98.00 |
| V2 | pulse | pwm_rand_output | 2.633m | 20.999ms | 49 | 50 | 98.00 |
| V2 | blink | pwm_rand_output | 2.633m | 20.999ms | 49 | 50 | 98.00 |
| V2 | heartbeat | pwm_rand_output | 2.633m | 20.999ms | 49 | 50 | 98.00 |
| V2 | resolution | pwm_rand_output | 2.633m | 20.999ms | 49 | 50 | 98.00 |
| V2 | multi_channel | pwm_rand_output | 2.633m | 20.999ms | 49 | 50 | 98.00 |
| V2 | polarity | pwm_rand_output | 2.633m | 20.999ms | 49 | 50 | 98.00 |
| V2 | phase | pwm_rand_output | 2.633m | 20.999ms | 49 | 50 | 98.00 |
| V2 | lowpower | pwm_rand_output | 2.633m | 20.999ms | 49 | 50 | 98.00 |
| V2 | perf | pwm_perf | 52.000s | 21.433ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 5.867m | 209.996ms | 49 | 50 | 98.00 |
| V2 | alert_test | pwm_alert_test | 13.000s | 27.294us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 9.000s | 12.615us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 8.000s | 172.538us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 8.000s | 172.538us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 8.000s | 35.252us | 5 | 5 | 100.00 |
| pwm_csr_rw | 17.000s | 279.827us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 13.000s | 422.514us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 13.000s | 67.301us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 8.000s | 35.252us | 5 | 5 | 100.00 |
| pwm_csr_rw | 17.000s | 279.827us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 13.000s | 422.514us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 13.000s | 67.301us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 7.000s | 72.169us | 20 | 20 | 100.00 |
| pwm_sec_cm | 4.000s | 148.896us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 7.000s | 72.169us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 417 | 420 | 99.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.60 | 99.62 | 99.32 | 99.96 | 95.13 | 94.92 | -- | 100.00 | 99.01 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test pwm_perf has 1 failures.
1.pwm_perf.55291092923667579185903521036800444381203358332454045540852948178705260682574
Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/1.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwm_rand_output has 1 failures.
27.pwm_rand_output.11692165804681808126045098253748134912744078492596384636484006560964096138287
Line 404, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/27.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:
49.pwm_stress_all.80153098198667619926485996972149027482488035366233302377642008587639010647130
Line 833, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/49.pwm_stress_all/latest/run.log
UVM_ERROR @ 53080456395 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 53080456395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---