PWM Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 5.000s 536.806us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 134.330us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 205.475us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 10.000s 1.814ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 87.136us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 3.000s 61.384us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 205.475us 20 20 100.00
pwm_csr_aliasing 4.000s 87.136us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 2.250m 42.004ms 50 50 100.00
V2 pulse pwm_rand_output 2.250m 42.004ms 50 50 100.00
V2 blink pwm_rand_output 2.250m 42.004ms 50 50 100.00
V2 heartbeat pwm_rand_output 2.250m 42.004ms 50 50 100.00
V2 resolution pwm_rand_output 2.250m 42.004ms 50 50 100.00
V2 multi_channel pwm_rand_output 2.250m 42.004ms 50 50 100.00
V2 polarity pwm_rand_output 2.250m 42.004ms 50 50 100.00
V2 phase pwm_rand_output 2.250m 42.004ms 50 50 100.00
V2 lowpower pwm_rand_output 2.250m 42.004ms 50 50 100.00
V2 perf pwm_perf 51.000s 10.611ms 49 50 98.00
V2 stress_all pwm_stress_all 6.283m 247.053ms 48 50 96.00
V2 alert_test pwm_alert_test 3.000s 25.159us 50 50 100.00
V2 intr_test pwm_intr_test 8.000s 38.098us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 140.030us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 140.030us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 134.330us 5 5 100.00
pwm_csr_rw 3.000s 205.475us 20 20 100.00
pwm_csr_aliasing 4.000s 87.136us 5 5 100.00
pwm_same_csr_outstanding 4.000s 95.418us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 134.330us 5 5 100.00
pwm_csr_rw 3.000s 205.475us 20 20 100.00
pwm_csr_aliasing 4.000s 87.136us 5 5 100.00
pwm_same_csr_outstanding 4.000s 95.418us 20 20 100.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err pwm_tl_intg_err 5.000s 1.265ms 20 20 100.00
pwm_sec_cm 3.000s 118.024us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 1.265ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 417 420 99.29

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 5 71.43
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.65 99.62 99.32 100.00 95.31 94.92 -- 100.00 99.01

Failure Buckets

Past Results