PWM Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	529.154us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	16.069us	5	5	100.00
V1	csr_rw	pwm_csr_rw	8.000s	17.327us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	7.000s	493.157us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	316.649us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	20.924us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	8.000s	17.327us	20	20	100.00
		pwm_csr_aliasing	4.000s	316.649us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.217m	21.004ms	50	50	100.00
V2	pulse	pwm_rand_output	1.217m	21.004ms	50	50	100.00
V2	blink	pwm_rand_output	1.217m	21.004ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.217m	21.004ms	50	50	100.00
V2	resolution	pwm_rand_output	1.217m	21.004ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.217m	21.004ms	50	50	100.00
V2	polarity	pwm_rand_output	1.217m	21.004ms	50	50	100.00
V2	phase	pwm_rand_output	1.217m	21.004ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.217m	21.004ms	50	50	100.00
V2	perf	pwm_perf	49.000s	10.505ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.467m	63.507ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	110.284us	50	50	100.00
V2	intr_test	pwm_intr_test	7.000s	23.633us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	10.000s	38.364us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	10.000s	38.364us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	16.069us	5	5	100.00
		pwm_csr_rw	8.000s	17.327us	20	20	100.00
		pwm_csr_aliasing	4.000s	316.649us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	165.926us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	16.069us	5	5	100.00
		pwm_csr_rw	8.000s	17.327us	20	20	100.00
		pwm_csr_aliasing	4.000s	316.649us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	165.926us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	312.563us	20	20	100.00
		pwm_sec_cm	4.000s	251.503us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	312.563us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.26	99.31	98.77	99.76	94.48	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

32.pwm_stress_all.66854899139100549947885836790631420410304807217052429729227569712187292073143
Line 600, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/32.pwm_stress_all/latest/run.log

  UVM_ERROR @ 11011185755 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 11011185755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.pwm_stress_all.44130171580294805977167814285728832323958414679372659980881366332176247328864
Line 11392740, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/39.pwm_stress_all/latest/run.log

  UVM_ERROR @ 30490857619 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [1] did not MATCH
  UVM_INFO @ 30490857619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---