PWM Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	1.018ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	4.000s	25.336us	5	5	100.00
V1	csr_rw	pwm_csr_rw	7.000s	19.137us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	9.000s	8.309ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	35.521us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	9.000s	18.487us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	7.000s	19.137us	20	20	100.00
		pwm_csr_aliasing	4.000s	35.521us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.267m	21.431ms	50	50	100.00
V2	pulse	pwm_rand_output	2.267m	21.431ms	50	50	100.00
V2	blink	pwm_rand_output	2.267m	21.431ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.267m	21.431ms	50	50	100.00
V2	resolution	pwm_rand_output	2.267m	21.431ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.267m	21.431ms	50	50	100.00
V2	polarity	pwm_rand_output	2.267m	21.431ms	50	50	100.00
V2	phase	pwm_rand_output	2.267m	21.431ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.267m	21.431ms	50	50	100.00
V2	perf	pwm_perf	51.000s	34.999ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.733m	76.562ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	14.177us	50	50	100.00
V2	intr_test	pwm_intr_test	12.000s	14.634us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	17.000s	256.613us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	17.000s	256.613us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	4.000s	25.336us	5	5	100.00
		pwm_csr_rw	7.000s	19.137us	20	20	100.00
		pwm_csr_aliasing	4.000s	35.521us	5	5	100.00
		pwm_same_csr_outstanding	8.000s	180.261us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	4.000s	25.336us	5	5	100.00
		pwm_csr_rw	7.000s	19.137us	20	20	100.00
		pwm_csr_aliasing	4.000s	35.521us	5	5	100.00
		pwm_same_csr_outstanding	8.000s	180.261us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	342.780us	20	20	100.00
		pwm_sec_cm	3.000s	510.027us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	342.780us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	99.76	99.57	100.00	95.54	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

3.pwm_stress_all.50297247943596394875128083926440192090911275947283889621015869028562698281133
Line 87914, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/3.pwm_stress_all/latest/run.log

  UVM_ERROR @ 48315953984 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 48315953984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwm_stress_all.92541155968653609741631515461180438679286963383276802458768363660640172449491
Line 1992, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/7.pwm_stress_all/latest/run.log

  UVM_ERROR @ 123130689661 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 123130689661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---