e971cd9798| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 10.000s | 1.040ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 84.294us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 17.735us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 592.767us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 3.000s | 110.439us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 82.291us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 17.735us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 3.000s | 110.439us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.550m | 200.000ms | 49 | 50 | 98.00 |
| V2 | pulse | pwm_rand_output | 1.550m | 200.000ms | 49 | 50 | 98.00 |
| V2 | blink | pwm_rand_output | 1.550m | 200.000ms | 49 | 50 | 98.00 |
| V2 | heartbeat | pwm_rand_output | 1.550m | 200.000ms | 49 | 50 | 98.00 |
| V2 | resolution | pwm_rand_output | 1.550m | 200.000ms | 49 | 50 | 98.00 |
| V2 | multi_channel | pwm_rand_output | 1.550m | 200.000ms | 49 | 50 | 98.00 |
| V2 | polarity | pwm_rand_output | 1.550m | 200.000ms | 49 | 50 | 98.00 |
| V2 | phase | pwm_rand_output | 1.550m | 200.000ms | 49 | 50 | 98.00 |
| V2 | lowpower | pwm_rand_output | 1.550m | 200.000ms | 49 | 50 | 98.00 |
| V2 | perf | pwm_perf | 54.000s | 65.623ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 4.167m | 242.338ms | 49 | 50 | 98.00 |
| V2 | alert_test | pwm_alert_test | 12.000s | 17.455us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 40.416us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 5.000s | 66.635us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 5.000s | 66.635us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 84.294us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 17.735us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 3.000s | 110.439us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 169.716us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 84.294us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 17.735us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 3.000s | 110.439us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 169.716us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 1.700ms | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 251.943us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 1.700ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 417 | 420 | 99.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.56 | 99.52 | 99.14 | 99.88 | 95.31 | 94.92 | -- | 100.00 | 99.01 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test pwm_perf has 1 failures.
26.pwm_perf.102199378900776030872828068123795409097628695748517943415201755973498774241517
Line 399, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/26.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwm_rand_output has 1 failures.
48.pwm_rand_output.34305619650792807135343317788351783369296291639899812292114985136791718280826
Line 5332896, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/48.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:
26.pwm_stress_all.32148924757610172625369496774463572583958883760438968641669752277473754736542
Line 10160, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/26.pwm_stress_all/latest/run.log
UVM_ERROR @ 22583865209 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 22583865209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---