PWM Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	1.023ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	100.899us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	26.455us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	1.905ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	84.669us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	153.417us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	26.455us	20	20	100.00
		pwm_csr_aliasing	4.000s	84.669us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.350m	11.938ms	48	50	96.00
V2	pulse	pwm_rand_output	1.350m	11.938ms	48	50	96.00
V2	blink	pwm_rand_output	1.350m	11.938ms	48	50	96.00
V2	heartbeat	pwm_rand_output	1.350m	11.938ms	48	50	96.00
V2	resolution	pwm_rand_output	1.350m	11.938ms	48	50	96.00
V2	multi_channel	pwm_rand_output	1.350m	11.938ms	48	50	96.00
V2	polarity	pwm_rand_output	1.350m	11.938ms	48	50	96.00
V2	phase	pwm_rand_output	1.350m	11.938ms	48	50	96.00
V2	lowpower	pwm_rand_output	1.350m	11.938ms	48	50	96.00
V2	perf	pwm_perf	52.000s	43.749ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.267m	264.588ms	47	50	94.00
V2	alert_test	pwm_alert_test	3.000s	40.896us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	45.721us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	47.017us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	47.017us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	100.899us	5	5	100.00
		pwm_csr_rw	3.000s	26.455us	20	20	100.00
		pwm_csr_aliasing	4.000s	84.669us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	181.702us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	100.899us	5	5	100.00
		pwm_csr_rw	3.000s	26.455us	20	20	100.00
		pwm_csr_aliasing	4.000s	84.669us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	181.702us	20	20	100.00
V2		TOTAL			285	290	98.28
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	438.442us	20	20	100.00
		pwm_sec_cm	3.000s	104.179us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	438.442us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			415	420	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.48	99.41	98.95	99.84	95.17	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:

Test pwm_stress_all has 3 failures.

30.pwm_stress_all.4573789869759291424678657998586208559737193583058590482629671469001976330802
Line 508, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/30.pwm_stress_all/latest/run.log

  UVM_ERROR @ 11054081566 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 11054081566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.pwm_stress_all.78607442317395341992960471298901130276029999997963679268496609490167183803050
Line 704, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/47.pwm_stress_all/latest/run.log

  UVM_ERROR @ 80804730482 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [4] did not MATCH
  UVM_INFO @ 80804730482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test pwm_rand_output has 2 failures.
  - 46.pwm_rand_output.32171529889108459996791762760557733745419326659567667849964077707422080827850
    Line 353, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/46.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.pwm_rand_output.37172268853256976538076243959659656009348020948719900699519363841032015841219
    Line 402, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/48.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```