PWM Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 10.000s 518.107us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 7.000s 118.368us 5 5 100.00
V1 csr_rw pwm_csr_rw 8.000s 15.548us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 952.800us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 3.000s 101.437us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 7.000s 36.902us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 8.000s 15.548us 20 20 100.00
pwm_csr_aliasing 3.000s 101.437us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 4.100m 47.720ms 49 50 98.00
V2 pulse pwm_rand_output 4.100m 47.720ms 49 50 98.00
V2 blink pwm_rand_output 4.100m 47.720ms 49 50 98.00
V2 heartbeat pwm_rand_output 4.100m 47.720ms 49 50 98.00
V2 resolution pwm_rand_output 4.100m 47.720ms 49 50 98.00
V2 multi_channel pwm_rand_output 4.100m 47.720ms 49 50 98.00
V2 polarity pwm_rand_output 4.100m 47.720ms 49 50 98.00
V2 phase pwm_rand_output 4.100m 47.720ms 49 50 98.00
V2 lowpower pwm_rand_output 4.100m 47.720ms 49 50 98.00
V2 perf pwm_perf 53.000s 47.716ms 50 50 100.00
V2 stress_all pwm_stress_all 4.350m 55.800ms 50 50 100.00
V2 alert_test pwm_alert_test 13.000s 16.623us 50 50 100.00
V2 intr_test pwm_intr_test 12.000s 18.623us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 9.000s 424.866us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 9.000s 424.866us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 7.000s 118.368us 5 5 100.00
pwm_csr_rw 8.000s 15.548us 20 20 100.00
pwm_csr_aliasing 3.000s 101.437us 5 5 100.00
pwm_same_csr_outstanding 12.000s 34.197us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 7.000s 118.368us 5 5 100.00
pwm_csr_rw 8.000s 15.548us 20 20 100.00
pwm_csr_aliasing 3.000s 101.437us 5 5 100.00
pwm_same_csr_outstanding 12.000s 34.197us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 9.000s 236.013us 20 20 100.00
pwm_sec_cm 7.000s 149.676us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 9.000s 236.013us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.56 99.52 99.14 99.92 95.24 94.92 -- 100.00 99.01

Failure Buckets

Past Results