c8985d6745
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 5.000s | 2.127ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 22.613us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 3.000s | 44.764us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 1.300ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 3.000s | 34.405us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 3.000s | 88.180us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 44.764us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 3.000s | 34.405us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 1.200m | 41.992ms | 50 | 50 | 100.00 |
V2 | pulse | pwm_rand_output | 1.200m | 41.992ms | 50 | 50 | 100.00 |
V2 | blink | pwm_rand_output | 1.200m | 41.992ms | 50 | 50 | 100.00 |
V2 | heartbeat | pwm_rand_output | 1.200m | 41.992ms | 50 | 50 | 100.00 |
V2 | resolution | pwm_rand_output | 1.200m | 41.992ms | 50 | 50 | 100.00 |
V2 | multi_channel | pwm_rand_output | 1.200m | 41.992ms | 50 | 50 | 100.00 |
V2 | polarity | pwm_rand_output | 1.200m | 41.992ms | 50 | 50 | 100.00 |
V2 | phase | pwm_rand_output | 1.200m | 41.992ms | 50 | 50 | 100.00 |
V2 | lowpower | pwm_rand_output | 1.200m | 41.992ms | 50 | 50 | 100.00 |
V2 | perf | pwm_perf | 51.000s | 10.827ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 4.600m | 76.560ms | 46 | 50 | 92.00 |
V2 | alert_test | pwm_alert_test | 7.000s | 49.813us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 3.000s | 14.604us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 5.000s | 105.886us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 5.000s | 105.886us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 22.613us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 44.764us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 3.000s | 34.405us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 99.513us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 22.613us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 44.764us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 3.000s | 34.405us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 99.513us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 286 | 290 | 98.62 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 8.000s | 1.197ms | 20 | 20 | 100.00 |
pwm_sec_cm | 3.000s | 239.003us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 8.000s | 1.197ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 416 | 420 | 99.05 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 6 | 85.71 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.53 | 99.59 | 99.26 | 100.00 | 94.79 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 4 failures:
13.pwm_stress_all.17338204870628003627322693495935936699089562710520799552836409524875828613823
Line 56497, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/13.pwm_stress_all/latest/run.log
UVM_ERROR @ 44906439564 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 44906439564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.pwm_stress_all.45620425414701052351604906394880590229567841166599590339870422541174218243919
Line 796804, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/17.pwm_stress_all/latest/run.log
UVM_ERROR @ 65351351486 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [3] did not MATCH
UVM_INFO @ 65351351486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.