PWM Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	515.771us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	17.250us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	17.762us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	501.056us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	3.000s	159.375us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	3.000s	158.912us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	17.762us	20	20	100.00
		pwm_csr_aliasing	3.000s	159.375us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.050m	11.805ms	49	50	98.00
V2	pulse	pwm_rand_output	1.050m	11.805ms	49	50	98.00
V2	blink	pwm_rand_output	1.050m	11.805ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.050m	11.805ms	49	50	98.00
V2	resolution	pwm_rand_output	1.050m	11.805ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.050m	11.805ms	49	50	98.00
V2	polarity	pwm_rand_output	1.050m	11.805ms	49	50	98.00
V2	phase	pwm_rand_output	1.050m	11.805ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.050m	11.805ms	49	50	98.00
V2	perf	pwm_perf	51.000s	87.483ms	49	50	98.00
V2	stress_all	pwm_stress_all	5.783m	67.389ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	17.952us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	28.238us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	119.762us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	119.762us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	17.250us	5	5	100.00
		pwm_csr_rw	3.000s	17.762us	20	20	100.00
		pwm_csr_aliasing	3.000s	159.375us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	108.660us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	17.250us	5	5	100.00
		pwm_csr_rw	3.000s	17.762us	20	20	100.00
		pwm_csr_aliasing	3.000s	159.375us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	108.660us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	119.298us	20	20	100.00
		pwm_sec_cm	2.000s	128.614us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	119.298us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			416	420	99.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.30	99.34	98.83	99.68	94.76	94.92	--	100.00	99.01

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test pwm_perf has 1 failures.
  - 8.pwm_perf.92848432601117840808777667729900699332564432281791181838934727193193943182170
    Line 399, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/8.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwm_rand_output has 1 failures.
  - 38.pwm_rand_output.102301892930245745925473173218193831137512685455629176300219349322889206468756
    Line 403, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/38.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

18.pwm_stress_all.83589285647060376018494410305450009491204230973243844740881507121603796832246
Line 150396, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/18.pwm_stress_all/latest/run.log

  UVM_ERROR @ 21103764354 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 21103764354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.pwm_stress_all.23937667236031260618393875692395265625016913088772160135654255010979056712563
Line 949, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/46.pwm_stress_all/latest/run.log

  UVM_ERROR @ 163481545514 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [3] did not MATCH
  UVM_INFO @ 163481545514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---