PWM Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 10.000s 1.131ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 4.000s 16.152us 5 5 100.00
V1 csr_rw pwm_csr_rw 4.000s 72.922us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 15.000s 467.026us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 6.000s 86.185us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 5.000s 500.628us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 4.000s 72.922us 20 20 100.00
pwm_csr_aliasing 6.000s 86.185us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.933m 10.609ms 50 50 100.00
V2 pulse pwm_rand_output 1.933m 10.609ms 50 50 100.00
V2 blink pwm_rand_output 1.933m 10.609ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.933m 10.609ms 50 50 100.00
V2 resolution pwm_rand_output 1.933m 10.609ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.933m 10.609ms 50 50 100.00
V2 polarity pwm_rand_output 1.933m 10.609ms 50 50 100.00
V2 phase pwm_rand_output 1.933m 10.609ms 50 50 100.00
V2 lowpower pwm_rand_output 1.933m 10.609ms 50 50 100.00
V2 perf pwm_perf 1.833m 42.006ms 50 50 100.00
V2 stress_all pwm_stress_all 8.117m 153.113ms 49 50 98.00
V2 alert_test pwm_alert_test 4.000s 22.917us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 33.137us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 7.000s 490.269us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 7.000s 490.269us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 4.000s 16.152us 5 5 100.00
pwm_csr_rw 4.000s 72.922us 20 20 100.00
pwm_csr_aliasing 6.000s 86.185us 5 5 100.00
pwm_same_csr_outstanding 5.000s 334.204us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 4.000s 16.152us 5 5 100.00
pwm_csr_rw 4.000s 72.922us 20 20 100.00
pwm_csr_aliasing 6.000s 86.185us 5 5 100.00
pwm_same_csr_outstanding 5.000s 334.204us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 6.000s 1.090ms 20 20 100.00
pwm_sec_cm 4.000s 406.573us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 6.000s 1.090ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.51 99.48 99.08 99.92 95.07 94.92 -- 100.00 99.01

Failure Buckets

Past Results