25b1acbf68| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 9.000s | 4.617ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 4.000s | 16.891us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 4.000s | 18.610us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 12.000s | 1.088ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 37.671us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 58.753us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 4.000s | 18.610us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 5.000s | 37.671us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 3.567m | 10.720ms | 50 | 50 | 100.00 |
| V2 | pulse | pwm_rand_output | 3.567m | 10.720ms | 50 | 50 | 100.00 |
| V2 | blink | pwm_rand_output | 3.567m | 10.720ms | 50 | 50 | 100.00 |
| V2 | heartbeat | pwm_rand_output | 3.567m | 10.720ms | 50 | 50 | 100.00 |
| V2 | resolution | pwm_rand_output | 3.567m | 10.720ms | 50 | 50 | 100.00 |
| V2 | multi_channel | pwm_rand_output | 3.567m | 10.720ms | 50 | 50 | 100.00 |
| V2 | polarity | pwm_rand_output | 3.567m | 10.720ms | 50 | 50 | 100.00 |
| V2 | phase | pwm_rand_output | 3.567m | 10.720ms | 50 | 50 | 100.00 |
| V2 | lowpower | pwm_rand_output | 3.567m | 10.720ms | 50 | 50 | 100.00 |
| V2 | perf | pwm_perf | 1.483m | 149.983ms | 47 | 50 | 94.00 |
| V2 | stress_all | pwm_stress_all | 5.783m | 125.989ms | 46 | 50 | 92.00 |
| V2 | alert_test | pwm_alert_test | 4.000s | 17.074us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 13.852us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 8.000s | 538.223us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 8.000s | 538.223us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 4.000s | 16.891us | 5 | 5 | 100.00 |
| pwm_csr_rw | 4.000s | 18.610us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 37.671us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 243.400us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 4.000s | 16.891us | 5 | 5 | 100.00 |
| pwm_csr_rw | 4.000s | 18.610us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 37.671us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 243.400us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 283 | 290 | 97.59 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 6.000s | 129.070us | 20 | 20 | 100.00 |
| pwm_sec_cm | 4.000s | 46.241us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 6.000s | 129.070us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 413 | 420 | 98.33 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.38 | 99.45 | 99.01 | 99.88 | 94.59 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 4 failures:
1.pwm_stress_all.99602486658809204820572876770075771482750927086636505013988821299267342062457
Line 7145030, in log /workspaces/repo/scratch/os_regression_2024_09_10/pwm-sim-xcelium/1.pwm_stress_all/latest/run.log
UVM_ERROR @ 51836644455 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [1] did not MATCH
UVM_INFO @ 51836644455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.pwm_stress_all.34593726883165743927970110133355468882570057551011127201748270989640223245772
Line 262606, in log /workspaces/repo/scratch/os_regression_2024_09_10/pwm-sim-xcelium/32.pwm_stress_all/latest/run.log
UVM_ERROR @ 134872668315 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 134872668315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
26.pwm_perf.39378565412121046455847532330535063543536184351198717482501641199924118893275
Line 138, in log /workspaces/repo/scratch/os_regression_2024_09_10/pwm-sim-xcelium/26.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.pwm_perf.93593952420690492355303991614666852906355357788665074908136311299292936587009
Line 192, in log /workspaces/repo/scratch/os_regression_2024_09_10/pwm-sim-xcelium/27.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.