PWM Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: XCELIUM

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	9.000s	6.363ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	4.000s	59.587us	5	5	100.00
V1	csr_rw	pwm_csr_rw	13.000s	40.217us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	12.000s	1.321ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	364.562us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	13.000s	29.479us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	13.000s	40.217us	20	20	100.00
		pwm_csr_aliasing	5.000s	364.562us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.850m	42.003ms	49	50	98.00
V2	pulse	pwm_rand_output	1.850m	42.003ms	49	50	98.00
V2	blink	pwm_rand_output	1.850m	42.003ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.850m	42.003ms	49	50	98.00
V2	resolution	pwm_rand_output	1.850m	42.003ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.850m	42.003ms	49	50	98.00
V2	polarity	pwm_rand_output	1.850m	42.003ms	49	50	98.00
V2	phase	pwm_rand_output	1.850m	42.003ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.850m	42.003ms	49	50	98.00
V2	perf	pwm_perf	1.700m	21.429ms	50	50	100.00
V2	stress_all	pwm_stress_all	6.967m	74.233ms	48	50	96.00
V2	alert_test	pwm_alert_test	4.000s	46.699us	50	50	100.00
V2	intr_test	pwm_intr_test	20.000s	19.800us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	14.000s	205.210us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	14.000s	205.210us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	4.000s	59.587us	5	5	100.00
		pwm_csr_rw	13.000s	40.217us	20	20	100.00
		pwm_csr_aliasing	5.000s	364.562us	5	5	100.00
		pwm_same_csr_outstanding	13.000s	38.711us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	4.000s	59.587us	5	5	100.00
		pwm_csr_rw	13.000s	40.217us	20	20	100.00
		pwm_csr_aliasing	5.000s	364.562us	5	5	100.00
		pwm_same_csr_outstanding	13.000s	38.711us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	7.000s	113.543us	20	20	100.00
		pwm_sec_cm	4.000s	80.731us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	7.000s	113.543us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.45	99.38	98.89	99.80	95.17	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

28.pwm_stress_all.37657101553802750405596412583542506059162768028408054748744260199920263142869
Line 2539784, in log /workspaces/repo/scratch/os_regression_2024_08_28/pwm-sim-xcelium/28.pwm_stress_all/latest/run.log

  UVM_ERROR @ 22645159612 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [2] did not MATCH
  UVM_INFO @ 22645159612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.pwm_stress_all.54651375687043658155192044696371440920821733260513889931510427546663997201097
Line 441, in log /workspaces/repo/scratch/os_regression_2024_08_28/pwm-sim-xcelium/34.pwm_stress_all/latest/run.log

  UVM_ERROR @ 12008779844 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 12008779844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_rand_output has 1 failures.
  - 12.pwm_rand_output.8819138564855727710797639583286752114520963868095334362183946700091803572450
    Line 216, in log /workspaces/repo/scratch/os_regression_2024_08_28/pwm-sim-xcelium/12.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```