PWM Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: XCELIUM

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	9.000s	513.056us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	4.000s	67.403us	5	5	100.00
V1	csr_rw	pwm_csr_rw	4.000s	38.091us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	9.000s	1.381ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	50.317us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	32.398us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	4.000s	38.091us	20	20	100.00
		pwm_csr_aliasing	4.000s	50.317us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	3.000m	22.343ms	50	50	100.00
V2	pulse	pwm_rand_output	3.000m	22.343ms	50	50	100.00
V2	blink	pwm_rand_output	3.000m	22.343ms	50	50	100.00
V2	heartbeat	pwm_rand_output	3.000m	22.343ms	50	50	100.00
V2	resolution	pwm_rand_output	3.000m	22.343ms	50	50	100.00
V2	multi_channel	pwm_rand_output	3.000m	22.343ms	50	50	100.00
V2	polarity	pwm_rand_output	3.000m	22.343ms	50	50	100.00
V2	phase	pwm_rand_output	3.000m	22.343ms	50	50	100.00
V2	lowpower	pwm_rand_output	3.000m	22.343ms	50	50	100.00
V2	perf	pwm_perf	1.500m	33.874ms	50	50	100.00
V2	stress_all	pwm_stress_all	7.567m	918.520ms	48	50	96.00
V2	alert_test	pwm_alert_test	4.000s	35.047us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	21.353us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	8.000s	44.404us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	8.000s	44.404us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	4.000s	67.403us	5	5	100.00
		pwm_csr_rw	4.000s	38.091us	20	20	100.00
		pwm_csr_aliasing	4.000s	50.317us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	106.341us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	4.000s	67.403us	5	5	100.00
		pwm_csr_rw	4.000s	38.091us	20	20	100.00
		pwm_csr_aliasing	4.000s	50.317us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	106.341us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	6.000s	84.149us	20	20	100.00
		pwm_sec_cm	4.000s	125.348us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	6.000s	84.149us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.56	99.59	99.26	99.92	95.10	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

43.pwm_stress_all.101815018543338368800925410023555082507748260083670254120310521783590375770900
Line 2506762, in log /workspaces/repo/scratch/os_regression_2024_08_26/pwm-sim-xcelium/43.pwm_stress_all/latest/run.log

  UVM_ERROR @ 47831030669 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [4] did not MATCH
  UVM_INFO @ 47831030669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.pwm_stress_all.35821898820324358924110145204749866180136996957963180486912309274076528470589
Line 1430, in log /workspaces/repo/scratch/os_regression_2024_08_26/pwm-sim-xcelium/48.pwm_stress_all/latest/run.log

  UVM_ERROR @ 41924341392 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 41924341392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---