PWM Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 9.000s 2.311ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 17.263us 5 5 100.00
V1 csr_rw pwm_csr_rw 20.000s 17.714us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 2.648ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 131.550us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 21.000s 31.578us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 20.000s 17.714us 20 20 100.00
pwm_csr_aliasing 5.000s 131.550us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.917m 45.648ms 50 50 100.00
V2 pulse pwm_rand_output 1.917m 45.648ms 50 50 100.00
V2 blink pwm_rand_output 1.917m 45.648ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.917m 45.648ms 50 50 100.00
V2 resolution pwm_rand_output 1.917m 45.648ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.917m 45.648ms 50 50 100.00
V2 polarity pwm_rand_output 1.917m 45.648ms 50 50 100.00
V2 phase pwm_rand_output 1.917m 45.648ms 50 50 100.00
V2 lowpower pwm_rand_output 1.917m 45.648ms 50 50 100.00
V2 perf pwm_perf 1.817m 45.647ms 50 50 100.00
V2 stress_all pwm_stress_all 5.517m 85.040ms 47 50 94.00
V2 alert_test pwm_alert_test 4.000s 32.357us 50 50 100.00
V2 intr_test pwm_intr_test 22.000s 91.206us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 18.000s 27.964us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 18.000s 27.964us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 17.263us 5 5 100.00
pwm_csr_rw 20.000s 17.714us 20 20 100.00
pwm_csr_aliasing 5.000s 131.550us 5 5 100.00
pwm_same_csr_outstanding 20.000s 32.977us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 17.263us 5 5 100.00
pwm_csr_rw 20.000s 17.714us 20 20 100.00
pwm_csr_aliasing 5.000s 131.550us 5 5 100.00
pwm_same_csr_outstanding 20.000s 32.977us 20 20 100.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err pwm_tl_intg_err 18.000s 46.427us 20 20 100.00
pwm_sec_cm 4.000s 140.371us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 18.000s 46.427us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 417 420 99.29

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.34 99.38 98.89 99.76 94.72 94.92 -- 100.00 99.01

Failure Buckets

Past Results