PWM Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	37.000s	1.155ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	14.000s	22.599us	5	5	100.00
V1	csr_rw	pwm_csr_rw	14.000s	33.730us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	18.000s	1.809ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	15.000s	473.816us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	20.000s	57.124us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	14.000s	33.730us	20	20	100.00
		pwm_csr_aliasing	15.000s	473.816us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.300m	21.877ms	50	50	100.00
V2	pulse	pwm_rand_output	2.300m	21.877ms	50	50	100.00
V2	blink	pwm_rand_output	2.300m	21.877ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.300m	21.877ms	50	50	100.00
V2	resolution	pwm_rand_output	2.300m	21.877ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.300m	21.877ms	50	50	100.00
V2	polarity	pwm_rand_output	2.300m	21.877ms	50	50	100.00
V2	phase	pwm_rand_output	2.300m	21.877ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.300m	21.877ms	50	50	100.00
V2	perf	pwm_perf	1.800m	10.504ms	49	50	98.00
V2	stress_all	pwm_stress_all	6.083m	63.007ms	49	50	98.00
V2	alert_test	pwm_alert_test	33.000s	29.606us	50	50	100.00
V2	intr_test	pwm_intr_test	22.000s	13.513us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	22.000s	309.086us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	22.000s	309.086us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	14.000s	22.599us	5	5	100.00
		pwm_csr_rw	14.000s	33.730us	20	20	100.00
		pwm_csr_aliasing	15.000s	473.816us	5	5	100.00
		pwm_same_csr_outstanding	14.000s	51.775us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	14.000s	22.599us	5	5	100.00
		pwm_csr_rw	14.000s	33.730us	20	20	100.00
		pwm_csr_aliasing	15.000s	473.816us	5	5	100.00
		pwm_same_csr_outstanding	14.000s	51.775us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	17.000s	69.310us	20	20	100.00
		pwm_sec_cm	20.000s	93.728us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	17.000s	69.310us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.28	99.24	98.65	99.80	94.65	94.92	--	100.00	99.01

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_perf has 1 failures.
  - 17.pwm_perf.104764224847541814639928899767504048559155876749330966207282388503839428002629
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_08_31/pwm-sim-xcelium/17.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:
- Test pwm_stress_all has 1 failures.
  - 43.pwm_stress_all.62385802845811913846026776489509169465606057741041402116635416307459972859492
    Line 72991, in log /workspaces/repo/scratch/os_regression_2024_08_31/pwm-sim-xcelium/43.pwm_stress_all/latest/run.log
```
  UVM_ERROR @ 41527099155 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [3] did not MATCH
  UVM_INFO @ 41527099155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

PWM Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ed1c41cd0f`