PWM Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 1.017m 1.040ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 4.000s 64.335us 5 5 100.00
V1 csr_rw pwm_csr_rw 4.000s 19.284us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 297.805us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 33.711us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 5.000s 54.916us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 4.000s 19.284us 20 20 100.00
pwm_csr_aliasing 5.000s 33.711us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.850m 11.938ms 50 50 100.00
V2 pulse pwm_rand_output 1.850m 11.938ms 50 50 100.00
V2 blink pwm_rand_output 1.850m 11.938ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.850m 11.938ms 50 50 100.00
V2 resolution pwm_rand_output 1.850m 11.938ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.850m 11.938ms 50 50 100.00
V2 polarity pwm_rand_output 1.850m 11.938ms 50 50 100.00
V2 phase pwm_rand_output 1.850m 11.938ms 50 50 100.00
V2 lowpower pwm_rand_output 1.850m 11.938ms 50 50 100.00
V2 perf pwm_perf 1.650m 21.430ms 50 50 100.00
V2 stress_all pwm_stress_all 6.350m 572.693ms 47 50 94.00
V2 alert_test pwm_alert_test 38.000s 14.082us 50 50 100.00
V2 intr_test pwm_intr_test 4.000s 31.821us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 8.000s 253.967us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 8.000s 253.967us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 4.000s 64.335us 5 5 100.00
pwm_csr_rw 4.000s 19.284us 20 20 100.00
pwm_csr_aliasing 5.000s 33.711us 5 5 100.00
pwm_same_csr_outstanding 5.000s 35.952us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 4.000s 64.335us 5 5 100.00
pwm_csr_rw 4.000s 19.284us 20 20 100.00
pwm_csr_aliasing 5.000s 33.711us 5 5 100.00
pwm_same_csr_outstanding 5.000s 35.952us 20 20 100.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err pwm_tl_intg_err 7.000s 607.571us 20 20 100.00
pwm_sec_cm 24.000s 332.217us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 7.000s 607.571us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 417 420 99.29

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.64 99.55 99.20 99.96 95.48 94.92 -- 100.00 99.01

Failure Buckets

Past Results