29d22a60a2| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 35.000s | 981.119us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 4.000s | 18.511us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 4.000s | 28.328us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 12.000s | 3.817ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 6.000s | 702.525us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 374.597us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 4.000s | 28.328us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 6.000s | 702.525us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 2.433m | 43.745ms | 50 | 50 | 100.00 |
| V2 | pulse | pwm_rand_output | 2.433m | 43.745ms | 50 | 50 | 100.00 |
| V2 | blink | pwm_rand_output | 2.433m | 43.745ms | 50 | 50 | 100.00 |
| V2 | heartbeat | pwm_rand_output | 2.433m | 43.745ms | 50 | 50 | 100.00 |
| V2 | resolution | pwm_rand_output | 2.433m | 43.745ms | 50 | 50 | 100.00 |
| V2 | multi_channel | pwm_rand_output | 2.433m | 43.745ms | 50 | 50 | 100.00 |
| V2 | polarity | pwm_rand_output | 2.433m | 43.745ms | 50 | 50 | 100.00 |
| V2 | phase | pwm_rand_output | 2.433m | 43.745ms | 50 | 50 | 100.00 |
| V2 | lowpower | pwm_rand_output | 2.433m | 43.745ms | 50 | 50 | 100.00 |
| V2 | perf | pwm_perf | 1.483m | 116.663ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 6.650m | 87.497ms | 47 | 50 | 94.00 |
| V2 | alert_test | pwm_alert_test | 39.000s | 42.222us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 4.000s | 14.707us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 47.912us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 47.912us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 4.000s | 18.511us | 5 | 5 | 100.00 |
| pwm_csr_rw | 4.000s | 28.328us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 6.000s | 702.525us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 5.000s | 57.456us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 4.000s | 18.511us | 5 | 5 | 100.00 |
| pwm_csr_rw | 4.000s | 28.328us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 6.000s | 702.525us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 5.000s | 57.456us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 261.831us | 20 | 20 | 100.00 |
| pwm_sec_cm | 33.000s | 61.426us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 261.831us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 416 | 420 | 99.05 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.27 | 99.31 | 98.77 | 99.72 | 94.62 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:
0.pwm_stress_all.106964668941748564605988241299583608941868697359018095558984647646055713370190
Line 3236949, in log /workspaces/repo/scratch/os_regression_2024_10_08/pwm-sim-xcelium/0.pwm_stress_all/latest/run.log
UVM_ERROR @ 112512188783 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 112512188783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pwm_stress_all.45435154149562826939980478713334218441027850643431162610356198910767245574466
Line 109769, in log /workspaces/repo/scratch/os_regression_2024_10_08/pwm-sim-xcelium/13.pwm_stress_all/latest/run.log
UVM_ERROR @ 133407145256 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [2] did not MATCH
UVM_INFO @ 133407145256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
4.pwm_perf.60393491476948431005628549320574464417691016314399811933167172708438661486344
Line 142, in log /workspaces/repo/scratch/os_regression_2024_10_08/pwm-sim-xcelium/4.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---