8a1401d614| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 9.000s | 529.545us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 4.000s | 26.126us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 4.000s | 40.724us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 1.039ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 265.040us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 24.632us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 4.000s | 40.724us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 5.000s | 265.040us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.550m | 10.718ms | 49 | 50 | 98.00 |
| V2 | pulse | pwm_rand_output | 1.550m | 10.718ms | 49 | 50 | 98.00 |
| V2 | blink | pwm_rand_output | 1.550m | 10.718ms | 49 | 50 | 98.00 |
| V2 | heartbeat | pwm_rand_output | 1.550m | 10.718ms | 49 | 50 | 98.00 |
| V2 | resolution | pwm_rand_output | 1.550m | 10.718ms | 49 | 50 | 98.00 |
| V2 | multi_channel | pwm_rand_output | 1.550m | 10.718ms | 49 | 50 | 98.00 |
| V2 | polarity | pwm_rand_output | 1.550m | 10.718ms | 49 | 50 | 98.00 |
| V2 | phase | pwm_rand_output | 1.550m | 10.718ms | 49 | 50 | 98.00 |
| V2 | lowpower | pwm_rand_output | 1.550m | 10.718ms | 49 | 50 | 98.00 |
| V2 | perf | pwm_perf | 1.417m | 10.940ms | 48 | 50 | 96.00 |
| V2 | stress_all | pwm_stress_all | 5.483m | 63.510ms | 49 | 50 | 98.00 |
| V2 | alert_test | pwm_alert_test | 4.000s | 35.263us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 51.978us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 66.558us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 66.558us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 4.000s | 26.126us | 5 | 5 | 100.00 |
| pwm_csr_rw | 4.000s | 40.724us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 265.040us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 146.470us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 4.000s | 26.126us | 5 | 5 | 100.00 |
| pwm_csr_rw | 4.000s | 40.724us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 265.040us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 146.470us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 6.000s | 166.490us | 20 | 20 | 100.00 |
| pwm_sec_cm | 4.000s | 85.012us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 6.000s | 166.490us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 416 | 420 | 99.05 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.47 | 99.52 | 99.14 | 99.88 | 94.86 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:
Test pwm_rand_output has 1 failures.
8.pwm_rand_output.48941277617286111985658791097003750836671231317502770477416980966557207779936
Line 146905, in log /workspaces/repo/scratch/os_regression_2024_10_11/pwm-sim-xcelium/8.pwm_rand_output/latest/run.log
UVM_ERROR @ 6670022558 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [2] did not MATCH
UVM_INFO @ 6670022558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwm_stress_all has 1 failures.
47.pwm_stress_all.38204761835844435843525778017255585823505535033662447158738349109296469379347
Line 3972278, in log /workspaces/repo/scratch/os_regression_2024_10_11/pwm-sim-xcelium/47.pwm_stress_all/latest/run.log
UVM_ERROR @ 195518846856 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [1] did not MATCH
UVM_INFO @ 195518846856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
9.pwm_perf.44993775193607817792497176144677640909763397725050321008807779700474787851751
Line 192, in log /workspaces/repo/scratch/os_regression_2024_10_11/pwm-sim-xcelium/9.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.pwm_perf.111338494062161594999389738252336852649920992177542899926274371477404825855132
Line 212, in log /workspaces/repo/scratch/os_regression_2024_10_11/pwm-sim-xcelium/26.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---