e3fb01b5e
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwrmgr_smoke | 0.750s | 29.714us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.710s | 75.292us | 5 | 5 | 100.00 |
V1 | csr_rw | pwrmgr_csr_rw | 0.710s | 27.645us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 2.710s | 261.412us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwrmgr_csr_aliasing | 0.970s | 627.802us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.320s | 269.819us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.710s | 27.645us | 20 | 20 | 100.00 |
pwrmgr_csr_aliasing | 0.970s | 627.802us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | wakeup | pwrmgr_wakeup | 1.430s | 227.959us | 50 | 50 | 100.00 |
V2 | control_clks | pwrmgr_wakeup | 1.430s | 227.959us | 50 | 50 | 100.00 |
V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.860s | 122.383us | 50 | 50 | 100.00 |
pwrmgr_lowpower_invalid | 0.830s | 44.809us | 50 | 50 | 100.00 | ||
V2 | reset | pwrmgr_reset | 1.220s | 78.484us | 50 | 50 | 100.00 |
pwrmgr_reset_invalid | 1.130s | 102.868us | 50 | 50 | 100.00 | ||
V2 | main_power_glitch_reset | pwrmgr_reset | 1.220s | 78.484us | 50 | 50 | 100.00 |
V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.620s | 347.508us | 50 | 50 | 100.00 |
V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.590s | 251.780us | 50 | 50 | 100.00 |
V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.980s | 53.326us | 50 | 50 | 100.00 |
V2 | stress_all | pwrmgr_stress_all | 9.820s | 1.931ms | 50 | 50 | 100.00 |
V2 | intr_test | pwrmgr_intr_test | 0.790s | 18.015us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.470s | 51.778us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.470s | 51.778us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.710s | 75.292us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.710s | 27.645us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 0.970s | 627.802us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.990s | 191.511us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.710s | 75.292us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.710s | 27.645us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 0.970s | 627.802us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.990s | 191.511us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 540 | 540 | 100.00 | |||
V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.620s | 175.273us | 20 | 20 | 100.00 |
pwrmgr_sec_cm | 1.980s | 626.684us | 5 | 5 | 100.00 | ||
V2S | prim_count_check | pwrmgr_sec_cm | 1.980s | 626.684us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | pwrmgr_sec_cm | 1.980s | 626.684us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.620s | 175.273us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 3.970s | 793.936us | 49 | 50 | 98.00 |
V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 4.170s | 851.363us | 50 | 50 | 100.00 |
V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 1.100s | 69.296us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.690s | 32.028us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 1.980s | 626.684us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 1.980s | 626.684us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 1.980s | 626.684us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.680s | 36.069us | 50 | 50 | 100.00 |
V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.720s | 59.505us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.700s | 276.292us | 50 | 50 | 100.00 |
V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.710s | 27.645us | 20 | 20 | 100.00 |
V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.710s | 27.645us | 20 | 20 | 100.00 |
V2S | TOTAL | 374 | 375 | 99.73 | |||
V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 37.400s | 10.857ms | 47 | 50 | 94.00 |
V3 | TOTAL | 47 | 50 | 94.00 | |||
TOTAL | 1066 | 1070 | 99.63 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 12 | 12 | 12 | 100.00 |
V2S | 9 | 9 | 8 | 88.89 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.93 | 98.21 | 96.58 | 99.44 | 96.00 | 96.27 | 100.00 | 99.02 |
Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
has 1 failures:
1.pwrmgr_stress_all_with_rand_reset.238954892
Line 2122, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log
Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
UVM_ERROR @ 6539813176 ps: (pwrmgr.sv:160) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
UVM_INFO @ 6539813176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.494968873
Line 667, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_FATAL @ 3000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 3000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:*
has 1 failures:
17.pwrmgr_stress_all_with_rand_reset.453326977
Line 2057, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 733451752 ps: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
UVM_INFO @ 733451752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])'
has 1 failures:
48.pwrmgr_stress_all_with_rand_reset.4064776714
Line 3650, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/48.pwrmgr_stress_all_with_rand_reset/latest/run.log
Offending '(((!esc_rst_req_d) && (fetch_en_o != On)) || slow_peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetEscIdx])'
UVM_ERROR @ 23690027058 ps: (pwrmgr.sv:155) [ASSERT FAILED] PwrmgrSecCmEscToSlowResetReq_A
UVM_INFO @ 23690027058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---