48542e748
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwrmgr_smoke | 0.720s | 26.836us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.670s | 30.345us | 5 | 5 | 100.00 |
V1 | csr_rw | pwrmgr_csr_rw | 0.710s | 20.569us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 2.000s | 112.575us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwrmgr_csr_aliasing | 0.960s | 75.891us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.530s | 128.623us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.710s | 20.569us | 20 | 20 | 100.00 |
pwrmgr_csr_aliasing | 0.960s | 75.891us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | wakeup | pwrmgr_wakeup | 1.630s | 235.255us | 50 | 50 | 100.00 |
V2 | control_clks | pwrmgr_wakeup | 1.630s | 235.255us | 50 | 50 | 100.00 |
V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.840s | 97.067us | 50 | 50 | 100.00 |
pwrmgr_lowpower_invalid | 0.790s | 45.892us | 50 | 50 | 100.00 | ||
V2 | reset | pwrmgr_reset | 1.410s | 85.193us | 50 | 50 | 100.00 |
pwrmgr_reset_invalid | 1.050s | 76.719us | 0 | 50 | 0.00 | ||
V2 | main_power_glitch_reset | pwrmgr_reset | 1.410s | 85.193us | 50 | 50 | 100.00 |
V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.830s | 338.466us | 50 | 50 | 100.00 |
V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.660s | 279.893us | 50 | 50 | 100.00 |
V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.950s | 68.559us | 50 | 50 | 100.00 |
V2 | stress_all | pwrmgr_stress_all | 11.810s | 3.415ms | 50 | 50 | 100.00 |
V2 | intr_test | pwrmgr_intr_test | 0.680s | 46.259us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.400s | 240.633us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.400s | 240.633us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.670s | 30.345us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.710s | 20.569us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 0.960s | 75.891us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.910s | 33.559us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.670s | 30.345us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.710s | 20.569us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 0.960s | 75.891us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.910s | 33.559us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 490 | 540 | 90.74 | |||
V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.700s | 593.061us | 20 | 20 | 100.00 |
pwrmgr_sec_cm | 2.420s | 785.744us | 5 | 5 | 100.00 | ||
V2S | prim_count_check | pwrmgr_sec_cm | 2.420s | 785.744us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | pwrmgr_sec_cm | 2.420s | 785.744us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.700s | 593.061us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 4.010s | 869.901us | 50 | 50 | 100.00 |
V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 4.340s | 909.002us | 50 | 50 | 100.00 |
V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 1.060s | 67.335us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.690s | 29.474us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 2.420s | 785.744us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 2.420s | 785.744us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 2.420s | 785.744us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.690s | 44.346us | 50 | 50 | 100.00 |
V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.760s | 48.885us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.800s | 291.735us | 50 | 50 | 100.00 |
V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.710s | 20.569us | 20 | 20 | 100.00 |
V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.710s | 20.569us | 20 | 20 | 100.00 |
V2S | TOTAL | 375 | 375 | 100.00 | |||
V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 48.710s | 11.391ms | 50 | 50 | 100.00 |
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 1020 | 1070 | 95.33 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 12 | 12 | 11 | 91.67 |
V2S | 9 | 9 | 9 | 100.00 |
V3 | 1 | 1 | 1 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
94.80 | 98.22 | 96.58 | 99.44 | 74.00 | 96.32 | 100.00 | 99.02 |
Offending '(fast_state == FastPwrStateRomCheckGood)'
has 50 failures:
0.pwrmgr_reset_invalid.2968589081
Line 244, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest/run.log
Offending '(fast_state == FastPwrStateRomCheckGood)'
UVM_ERROR @ 115014495 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
UVM_INFO @ 115014495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_reset_invalid.1348533309
Line 442, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest/run.log
Offending '(fast_state == FastPwrStateRomCheckGood)'
UVM_ERROR @ 68006068 ps: (pwrmgr_sec_cm_checker_assert.sv:69) [ASSERT FAILED] RomAllowCheckGoodState_A
UVM_INFO @ 68006068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.