ROM_CTRL Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	32.990s	7.787ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.600s	4.179ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.590s	2.437ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.260s	3.947ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.630s	2.106ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.760s	8.233ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.590s	2.437ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.630s	2.106ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.360s	2.051ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.270s	2.200ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.540s	12.586ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.642m	28.968ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.330s	4.258ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.760s	2.152ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.140s	2.037ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.140s	2.037ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.600s	4.179ms	5	5	100.00
		rom_ctrl_csr_rw	14.590s	2.437ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.630s	2.106ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.060s	2.069ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.600s	4.179ms	5	5	100.00
		rom_ctrl_csr_rw	14.590s	2.437ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.630s	2.106ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.060s	2.069ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.958m	63.372ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.145m	77.408ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.670m	5.905ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.236m	9.396ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.670m	5.905ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.958m	63.372ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.958m	63.372ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.958m	63.372ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.958m	63.372ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.958m	63.372ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.670m	5.905ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.670m	5.905ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	32.990s	7.787ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	32.990s	7.787ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	32.990s	7.787ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.236m	9.396ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.958m	63.372ms	48	50	96.00
		rom_ctrl_kmac_err_chk	30.330s	4.258ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.958m	63.372ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.958m	63.372ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.958m	63.372ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.145m	77.408ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.670m	5.905ms	5	5	100.00
V2S		TOTAL			92	95	96.84
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.442h	79.257ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			478	500	95.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.63	97.16	92.68	97.88	86.67	98.36	98.04	98.61

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 11 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.4008535282
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8da95683-3b68-4baf-84ca-821da0be3039
```
  - 6.rom_ctrl_stress_all_with_rand_reset.3394759314
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:0105ba77-11c9-4b0c-8832-9ec45bc1740e
```
  - ... and 9 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 7 failures:

Test rom_ctrl_smoke has 2 failures.

5.rom_ctrl_smoke.3424156715
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10013286676 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x6c381598
  UVM_INFO @ 10013286676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.rom_ctrl_smoke.197322128
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/29.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10005021770 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x68781732
  UVM_INFO @ 10005021770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

10.rom_ctrl_stress_all_with_rand_reset.2040597822
Line 222, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10057941116 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xfe8b397f
  UVM_INFO @ 10057941116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.rom_ctrl_stress_all_with_rand_reset.2990397716
Line 222, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10119972638 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x80975223
  UVM_INFO @ 10119972638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rom_ctrl_stress_all has 1 failures.

30.rom_ctrl_stress_all.1202952481
Line 220, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/30.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10065101459 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xb85513ae
  UVM_INFO @ 10065101459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 15.rom_ctrl_passthru_mem_tl_intg_err.1578537959
    Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/15.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 10008136555 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x307d8000
  UVM_INFO @ 10008136555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 23.rom_ctrl_corrupt_sig_fatal_chk.2642201126
    Line 225, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/23.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 908528612 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 908528612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 30.rom_ctrl_corrupt_sig_fatal_chk.3969689606
    Line 233, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/30.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 32.rom_ctrl_stress_all_with_rand_reset.3996167989
    Line 751, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/32.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 711755178002 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 711755178002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```