748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 45.370s | 8.570ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 17.170s | 6.115ms | 5 | 5 | 100.00 |
| V1 | csr_rw | rom_ctrl_csr_rw | 17.140s | 25.051ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 15.730s | 6.188ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 14.960s | 1.863ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 16.880s | 2.030ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 17.140s | 25.051ms | 20 | 20 | 100.00 |
| rom_ctrl_csr_aliasing | 14.960s | 1.863ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | rom_ctrl_mem_walk | 14.050s | 10.530ms | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 15.270s | 1.886ms | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 16.790s | 4.500ms | 48 | 50 | 96.00 |
| V2 | stress_all | rom_ctrl_stress_all | 2.609m | 15.313ms | 49 | 50 | 98.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 34.000s | 16.374ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 16.590s | 2.047ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 19.880s | 2.069ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 19.880s | 2.069ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 17.170s | 6.115ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 17.140s | 25.051ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 14.960s | 1.863ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 15.650s | 9.190ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 17.170s | 6.115ms | 5 | 5 | 100.00 |
| rom_ctrl_csr_rw | 17.140s | 25.051ms | 20 | 20 | 100.00 | ||
| rom_ctrl_csr_aliasing | 14.960s | 1.863ms | 5 | 5 | 100.00 | ||
| rom_ctrl_same_csr_outstanding | 15.650s | 9.190ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 237 | 240 | 98.75 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 9.411m | 123.856ms | 46 | 50 | 92.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 6.059m | 38.803ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | rom_ctrl_sec_cm | 1.981m | 6.772ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 1.458m | 883.696us | 20 | 20 | 100.00 | ||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 1.981m | 6.772ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.411m | 123.856ms | 46 | 50 | 92.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.411m | 123.856ms | 46 | 50 | 92.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 9.411m | 123.856ms | 46 | 50 | 92.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.411m | 123.856ms | 46 | 50 | 92.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.411m | 123.856ms | 46 | 50 | 92.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 1.981m | 6.772ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 1.981m | 6.772ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 45.370s | 8.570ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 45.370s | 8.570ms | 49 | 50 | 98.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 45.370s | 8.570ms | 49 | 50 | 98.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 1.458m | 883.696us | 20 | 20 | 100.00 |
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 9.411m | 123.856ms | 46 | 50 | 92.00 |
| rom_ctrl_kmac_err_chk | 34.000s | 16.374ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 9.411m | 123.856ms | 46 | 50 | 92.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 9.411m | 123.856ms | 46 | 50 | 92.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 9.411m | 123.856ms | 46 | 50 | 92.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 6.059m | 38.803ms | 19 | 20 | 95.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 1.981m | 6.772ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 90 | 95 | 94.74 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.567h | 162.874ms | 35 | 50 | 70.00 |
| V3 | TOTAL | 35 | 50 | 70.00 | |||
| TOTAL | 476 | 500 | 95.20 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 6 | 6 | 4 | 66.67 |
| V2S | 4 | 4 | 2 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.54 | 97.11 | 92.83 | 97.88 | 100.00 | 98.69 | 97.89 | 98.38 |
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
4.rom_ctrl_stress_all_with_rand_reset.29402818399979423045619591838872320187095994287394918606283430966105104444868
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8b36bcc8-490b-4e58-bdd2-ed98c1fe9a83
10.rom_ctrl_stress_all_with_rand_reset.45004076688294588594753614366017708889908590828035050390205786794833015470454
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:ee175d6d-173e-43b9-96a2-59f484a955b4
... and 11 more failures.
49.rom_ctrl_smoke.49411815706507007054363187956441578729070199607480009907733605238914921041708
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/49.rom_ctrl_smoke/latest/run.log
Job ID: smart:c373e53d-99f0-48e5-9475-eaae0d96811b
Exit reason: Error: User command failed Job returned non-zero exit code has 7 failures:
Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.
14.rom_ctrl_corrupt_sig_fatal_chk.39762267657066147458152438058307858694072442736359693798088591119716478421825
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
[make]: simulate
cd /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest && /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196914497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.3196914497
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
26.rom_ctrl_corrupt_sig_fatal_chk.112923903368428498320298384308254043465391119728069689824837193667771633979361
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/26.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
[make]: simulate
cd /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest && /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728611809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.2728611809
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 2 more failures.
Test rom_ctrl_max_throughput_chk has 2 failures.
15.rom_ctrl_max_throughput_chk.65686522022240379200058388736454180145831794143705213406686292681135135541876
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/15.rom_ctrl_max_throughput_chk/latest/run.log
[make]: simulate
cd /workspace/15.rom_ctrl_max_throughput_chk/latest && /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357793908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1357793908
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
17.rom_ctrl_max_throughput_chk.97354036885641102687025818924303621454306407388750223277351282021747555978324
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/17.rom_ctrl_max_throughput_chk/latest/run.log
[make]: simulate
cd /workspace/17.rom_ctrl_max_throughput_chk/latest && /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446923348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1446923348
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:35 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rom_ctrl_stress_all has 1 failures.
27.rom_ctrl_stress_all.46277426273914745541006393256122444233651094599598256222248698957644443888589
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/27.rom_ctrl_stress_all/latest/run.log
[make]: simulate
cd /workspace/27.rom_ctrl_stress_all/latest && /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633285581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.633285581
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
11.rom_ctrl_stress_all_with_rand_reset.76693756398696988537185643287751614063853338297292860809753205116616789466050
Line 258, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11417131701 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x446e6762
UVM_INFO @ 11417131701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.rom_ctrl_stress_all_with_rand_reset.95012558261659034280694183285793361801367349623154336209695524303822441437116
Line 276, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/31.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 38009350436 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x24dae79e
UVM_INFO @ 38009350436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
17.rom_ctrl_passthru_mem_tl_intg_err.9105621276836549224194149685574191040925443129699860793645392556426220364097
Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/17.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_FATAL @ 10007111939 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xfe73800c
UVM_INFO @ 10007111939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---