ROM_CTRL/64KB Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 1.345m 16.549ms 50 50 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 0 5 0.00
V1 csr_rw rom_ctrl_csr_rw 0 20 0.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 0 5 0.00
V1 csr_aliasing rom_ctrl_csr_aliasing 0 5 0.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 0 20 0.00
rom_ctrl_csr_aliasing 0 5 0.00
V1 mem_walk rom_ctrl_mem_walk 0 5 0.00
V1 mem_partial_access rom_ctrl_mem_partial_access 0 5 0.00
V1 TOTAL 50 115 43.48
V2 max_throughput_chk rom_ctrl_max_throughput_chk 36.520s 8.604ms 50 50 100.00
V2 stress_all rom_ctrl_stress_all 3.968m 32.190ms 50 50 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 1.166m 8.785ms 50 50 100.00
V2 alert_test rom_ctrl_alert_test 33.670s 8.871ms 50 50 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 0 20 0.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 0 20 0.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 0 5 0.00
rom_ctrl_csr_rw 0 20 0.00
rom_ctrl_csr_aliasing 0 5 0.00
rom_ctrl_same_csr_outstanding 0 20 0.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 0 5 0.00
rom_ctrl_csr_rw 0 20 0.00
rom_ctrl_csr_aliasing 0 5 0.00
rom_ctrl_same_csr_outstanding 0 20 0.00
V2 TOTAL 200 240 83.33
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 15.811m 286.176ms 50 50 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 0 20 0.00
V2S tl_intg_err rom_ctrl_sec_cm 4.004m 6.667ms 5 5 100.00
rom_ctrl_tl_intg_err 0 20 0.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.004m 6.667ms 5 5 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 15.811m 286.176ms 50 50 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 15.811m 286.176ms 50 50 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 15.811m 286.176ms 50 50 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 15.811m 286.176ms 50 50 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 15.811m 286.176ms 50 50 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.004m 6.667ms 5 5 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.004m 6.667ms 5 5 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 1.345m 16.549ms 50 50 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 1.345m 16.549ms 50 50 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 1.345m 16.549ms 50 50 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 0 20 0.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 15.811m 286.176ms 50 50 100.00
rom_ctrl_kmac_err_chk 1.166m 8.785ms 50 50 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 15.811m 286.176ms 50 50 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 15.811m 286.176ms 50 50 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 15.811m 286.176ms 50 50 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 0 20 0.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.004m 6.667ms 5 5 100.00
V2S TOTAL 55 95 57.89
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.091h 69.267ms 9 50 18.00
V3 TOTAL 9 50 18.00
TOTAL 314 500 62.80

Testplan Progress

Items Total Written Passing Progress
V1 8 8 1 12.50
V2 6 6 4 66.67
V2S 4 4 2 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.59 96.96 92.97 97.88 100.00 98.36 97.89 99.07

Failure Buckets

Past Results