1c75f24e99| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rom_ctrl_smoke | 1.345m | 16.549ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rom_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rom_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | rom_ctrl_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | rom_ctrl_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 50 | 115 | 43.48 | |||
| V2 | max_throughput_chk | rom_ctrl_max_throughput_chk | 36.520s | 8.604ms | 50 | 50 | 100.00 |
| V2 | stress_all | rom_ctrl_stress_all | 3.968m | 32.190ms | 50 | 50 | 100.00 |
| V2 | kmac_err_chk | rom_ctrl_kmac_err_chk | 1.166m | 8.785ms | 50 | 50 | 100.00 |
| V2 | alert_test | rom_ctrl_alert_test | 33.670s | 8.871ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rom_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rom_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| rom_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| rom_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| rom_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 200 | 240 | 83.33 | |||
| V2S | corrupt_sig_fatal_chk | rom_ctrl_corrupt_sig_fatal_chk | 15.811m | 286.176ms | 50 | 50 | 100.00 |
| V2S | passthru_mem_tl_intg_err | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | rom_ctrl_sec_cm | 4.004m | 6.667ms | 5 | 5 | 100.00 |
| rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | prim_fsm_check | rom_ctrl_sec_cm | 4.004m | 6.667ms | 5 | 5 | 100.00 |
| V2S | sec_cm_checker_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 15.811m | 286.176ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 15.811m | 286.176ms | 50 | 50 | 100.00 |
| V2S | sec_cm_checker_fsm_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 15.811m | 286.176ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctrl_flow_consistency | rom_ctrl_corrupt_sig_fatal_chk | 15.811m | 286.176ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_consistency | rom_ctrl_corrupt_sig_fatal_chk | 15.811m | 286.176ms | 50 | 50 | 100.00 |
| V2S | sec_cm_compare_ctr_redun | rom_ctrl_sec_cm | 4.004m | 6.667ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | rom_ctrl_sec_cm | 4.004m | 6.667ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_scramble | rom_ctrl_smoke | 1.345m | 16.549ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_digest | rom_ctrl_smoke | 1.345m | 16.549ms | 50 | 50 | 100.00 |
| V2S | sec_cm_intersig_mubi | rom_ctrl_smoke | 1.345m | 16.549ms | 50 | 50 | 100.00 |
| V2S | sec_cm_bus_integrity | rom_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bus_local_esc | rom_ctrl_corrupt_sig_fatal_chk | 15.811m | 286.176ms | 50 | 50 | 100.00 |
| rom_ctrl_kmac_err_chk | 1.166m | 8.785ms | 50 | 50 | 100.00 | ||
| V2S | sec_cm_mux_mubi | rom_ctrl_corrupt_sig_fatal_chk | 15.811m | 286.176ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mux_consistency | rom_ctrl_corrupt_sig_fatal_chk | 15.811m | 286.176ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_redun | rom_ctrl_corrupt_sig_fatal_chk | 15.811m | 286.176ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_mem_integrity | rom_ctrl_passthru_mem_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_tlul_fifo_ctr_redun | rom_ctrl_sec_cm | 4.004m | 6.667ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 55 | 95 | 57.89 | |||
| V3 | stress_all_with_rand_reset | rom_ctrl_stress_all_with_rand_reset | 2.091h | 69.267ms | 9 | 50 | 18.00 |
| V3 | TOTAL | 9 | 50 | 18.00 | |||
| TOTAL | 314 | 500 | 62.80 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 1 | 12.50 |
| V2 | 6 | 6 | 4 | 66.67 |
| V2S | 4 | 4 | 2 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.59 | 96.96 | 92.97 | 97.88 | 100.00 | 98.36 | 97.89 | 99.07 |
Job killed most likely because its dependent job failed. has 145 failures:
0.rom_ctrl_passthru_mem_tl_intg_err.90918755571665823549339370078511413770518843265308958078230391710447503661566
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
1.rom_ctrl_passthru_mem_tl_intg_err.33446980287376338593386375707181196715884843884749108311144280408001448282210
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
... and 18 more failures.
0.rom_ctrl_tl_errors.76627927609057982991588720947778909676053718498011718163647528165103135436639
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_tl_errors/latest/run.log
1.rom_ctrl_tl_errors.47076256442450159586955579416960975966807327156966703813460532228335111512476
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_tl_errors/latest/run.log
... and 18 more failures.
0.rom_ctrl_tl_intg_err.90829650891017567438574957862616632633529450119080901393085564216015420257191
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_tl_intg_err/latest/run.log
1.rom_ctrl_tl_intg_err.81869802559809045024842935897661444241124195729676583023950330701758036478413
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_tl_intg_err/latest/run.log
... and 18 more failures.
0.rom_ctrl_mem_walk.13409077746117031649281491724382739886025631364855406648604150477675833864471
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_mem_walk/latest/run.log
1.rom_ctrl_mem_walk.90394940589075899182242670947649933013384703403439678915381387639383811106747
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_mem_walk/latest/run.log
... and 3 more failures.
0.rom_ctrl_mem_partial_access.108343486433713496120632865554541932013656359870720653469550816594235500366607
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_mem_partial_access/latest/run.log
1.rom_ctrl_mem_partial_access.101039716619115829444069652288011793889726748371277535044357971287637485738603
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_mem_partial_access/latest/run.log
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
4.rom_ctrl_stress_all_with_rand_reset.30504662678215982366755238833520042801641070745090094170785270765464067415952
Line 530, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 33294519472 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 33294519472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rom_ctrl_stress_all_with_rand_reset.84934755305680036253695984308228973372401728931229350929928497846377380941111
Line 257, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1316570687 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1316570687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 8 failures:
11.rom_ctrl_stress_all_with_rand_reset.57438900109763833919182489655345630085889725390826691214980099200211664558800
Line 284, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 22405959412 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x554a91f2
UVM_INFO @ 22405959412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rom_ctrl_stress_all_with_rand_reset.59253516860542081994657636983237022019866823258741757750546840704930587159119
Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10005077691 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xd1fccdb1
UVM_INFO @ 10005077691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
1.rom_ctrl_stress_all_with_rand_reset.47979880840135728699426066758741623773474569159904609658760623795375348781650
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:996d9c06-47f4-43bb-84fe-9623f84d2ee9
16.rom_ctrl_stress_all_with_rand_reset.31006434844966562228298565262098434847316252344725744651729679936428494575873
Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:d5dc6aac-336c-4cd1-9230-fab2647335c5
... and 4 more failures.
tar (child): /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/cover_reg_top/output.tar.gz: Cannot open: No such file or directory tar (child): Error is not recoverable: exiting now tar: Child returned status * tar: Error is not recoverable: exiting now has 1 failures: