ROM_CTRL/32KB Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.100s	17.824ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.300s	8.868ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.770s	7.797ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.990s	2.132ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.480s	8.345ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.940s	13.848ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.770s	7.797ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.480s	8.345ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	13.640s	6.592ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.520s	8.346ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.630s	2.052ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.960m	81.784ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.480s	4.456ms	49	50	98.00
V2	alert_test	rom_ctrl_alert_test	16.920s	34.721ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.710s	3.975ms	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.710s	3.975ms	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.300s	8.868ms	5	5	100.00
		rom_ctrl_csr_rw	15.770s	7.797ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.480s	8.345ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.850s	2.127ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.300s	8.868ms	5	5	100.00
		rom_ctrl_csr_rw	15.770s	7.797ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.480s	8.345ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.850s	2.127ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	13.663m	525.895ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.735m	53.320ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.747m	4.545ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.288m	3.588ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.747m	4.545ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.663m	525.895ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.663m	525.895ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	13.663m	525.895ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.663m	525.895ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.663m	525.895ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.747m	4.545ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.747m	4.545ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.100s	17.824ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.100s	17.824ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.100s	17.824ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.288m	3.588ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	13.663m	525.895ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.480s	4.456ms	49	50	98.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	13.663m	525.895ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.663m	525.895ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	13.663m	525.895ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.735m	53.320ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.747m	4.545ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.115h	282.803ms	8	50	16.00
V3		TOTAL			8	50	16.00
		TOTAL			456	500	91.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	4	66.67
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	96.97	93.01	97.88	100.00	98.69	98.03	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 29 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.86823986601178101693490934120505974927792093309749927914518816473702523837985
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 460410933 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 460410933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.23579215411249643130748389723806106254602822603997158155459457997629661720527
    Line 439, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 81162036105 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 81162036105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 11 failures.
  - 12.rom_ctrl_stress_all_with_rand_reset.89862862550882170850745424669233276979722466499345441636833299537069838480944
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:98c979fe-805d-4b08-8369-7eb0f2081d60
```
  - 15.rom_ctrl_stress_all_with_rand_reset.89234476437282536313639326201045783535470312526551751021915811619124681699917
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:1c659818-c149-4ac7-a764-3aa8a6d6ec89
```
  - ... and 9 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:
- Test rom_ctrl_kmac_err_chk has 1 failures.
  - 14.rom_ctrl_kmac_err_chk.109117380691870388437250672365925049790561899972713828391587650543250145578448
    Line 251, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/14.rom_ctrl_kmac_err_chk/latest/run.log
```
  UVM_ERROR @ 3315688505 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 3315688505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_ctrl_tl_errors has 1 failures.
  - 16.rom_ctrl_tl_errors.17283755776721915221117349752343619490416673633027319483867970323475010535922
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 1657093133 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1657093133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 20.rom_ctrl_stress_all_with_rand_reset.91870183092468839950771712056685609221228248236337918744456954941314204684759
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/20.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10011136754 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xbea9a939
  UVM_INFO @ 10011136754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.rom_ctrl_stress_all_with_rand_reset.50404573754434198254771185146478540303242392762540478200775212233374738379138
    Line 299, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 42354422732 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x7dfe335b
  UVM_INFO @ 42354422732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `ecd9f08747`