ROM_CTRL/32KB Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: `f92a5ee77b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.330s	4.359ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.080s	6.752ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.770s	4.198ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.870s	1.885ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.510s	4.150ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.620s	8.420ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.770s	4.198ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.510s	4.150ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.300s	1.822ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.400s	3.470ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.880s	8.196ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.651m	42.034ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.470s	7.347ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	18.180s	7.965ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.560s	2.161ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.560s	2.161ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.080s	6.752ms	5	5	100.00
		rom_ctrl_csr_rw	16.770s	4.198ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.510s	4.150ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.220s	2.135ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.080s	6.752ms	5	5	100.00
		rom_ctrl_csr_rw	16.770s	4.198ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.510s	4.150ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.220s	2.135ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.281m	221.211ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.567m	47.503ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	59.490s	1.175ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.351m	2.723ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	59.490s	1.175ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.281m	221.211ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.281m	221.211ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.281m	221.211ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.281m	221.211ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.281m	221.211ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	59.490s	1.175ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	59.490s	1.175ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.330s	4.359ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.330s	4.359ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.330s	4.359ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.351m	2.723ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.281m	221.211ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.470s	7.347ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.281m	221.211ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.281m	221.211ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.281m	221.211ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.567m	47.503ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	59.490s	1.175ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.455h	161.804ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			469	500	93.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.24	96.89	91.99	97.72	100.00	98.28	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 25 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.39557313169529551636838875064731521041482251443447356693241393079527991799266
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 311595124 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 311595124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.92728121753083459815559134926396035888683330126288204176397752463873701799189
    Line 379, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9556689190 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9556689190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.88493554605716455049556229883428373256668228946421980789962202589236125397456
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:83b580a0-0c8c-4d6f-94c4-2ce2b519b515
```
  - 10.rom_ctrl_stress_all_with_rand_reset.24567236981936704701764689866941315641407569050237010560453677412882705864254
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:4da5e9aa-8516-473e-afe4-89539b322bae
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 22.rom_ctrl_stress_all_with_rand_reset.78788210706058365950292769740188817525379141858677926656522705061195991992526
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/22.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10010111950 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x56857cde
  UVM_INFO @ 10010111950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Sunday June 09 2024 19:02:32 UTC

GitHub Revision: f92a5ee77b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 74888572473032497941251936200792687439223302665780333354656685678472336958420

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `f92a5ee77b`