ROM_CTRL/32KB Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	44.930s	7.916ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.450s	2.193ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.940s	30.929ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.850s	7.368ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.340s	2.054ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.640s	1.885ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.940s	30.929ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.340s	2.054ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.220s	2.008ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.320s	3.999ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.180s	2.094ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.876m	49.598ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.410s	4.348ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.490s	8.691ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.260s	4.513ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.260s	4.513ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.450s	2.193ms	5	5	100.00
		rom_ctrl_csr_rw	14.940s	30.929ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.340s	2.054ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.910s	4.021ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.450s	2.193ms	5	5	100.00
		rom_ctrl_csr_rw	14.940s	30.929ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.340s	2.054ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.910s	4.021ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	10.318m	64.973ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.609m	11.394ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.869m	1.280ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.291m	1.713ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.869m	1.280ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.318m	64.973ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.318m	64.973ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.318m	64.973ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.318m	64.973ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.318m	64.973ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.869m	1.280ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.869m	1.280ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	44.930s	7.916ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	44.930s	7.916ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	44.930s	7.916ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.291m	1.713ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	10.318m	64.973ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.410s	4.348ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	10.318m	64.973ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	10.318m	64.973ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	10.318m	64.973ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.609m	11.394ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.869m	1.280ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.728h	225.781ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			468	500	93.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	96.97	93.02	97.88	100.00	98.37	98.04	98.83

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 23 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.64363496804604770339885647392517347291242284150286684613006959916153076955100
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 115376782 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 115376782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.2194654093980771578290623449346739492572627108302109632508684929764043031074
    Line 594, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 164855242409 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 164855242409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 13.rom_ctrl_stress_all_with_rand_reset.49836506179665563309711163432147802355096276151641999589262020398103526495231
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:24ad60b9-e950-4d84-9e7d-017b6a620cb1
```
  - 21.rom_ctrl_stress_all_with_rand_reset.109495525236755413493267769973666971917639468959059822461703372021752888329999
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/21.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:afb2f4a7-24f9-497a-8129-1d2aba57cd1d
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.93932183093989294923772045677997041990181496966094523993268384004564447655555
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10013695752 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc3020b1e
  UVM_INFO @ 10013695752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.rom_ctrl_stress_all_with_rand_reset.30255411971693813241944463737699308076931157723441958837464336647882085170314
    Line 270, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 22861325187 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xfed3ffe
  UVM_INFO @ 22861325187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0e5093d709`