ROM_CTRL/32KB Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	45.110s	32.851ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.710s	1.724ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.330s	2.109ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.130s	1.037ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.920s	3.206ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.170s	2.732ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.330s	2.109ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.920s	3.206ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.490s	3.445ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	16.090s	8.666ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.120s	6.455ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.814m	13.368ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	36.390s	39.042ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.720s	2.314ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.640s	1.808ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.640s	1.808ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.710s	1.724ms	5	5	100.00
		rom_ctrl_csr_rw	17.330s	2.109ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.920s	3.206ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.120s	4.020ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.710s	1.724ms	5	5	100.00
		rom_ctrl_csr_rw	17.330s	2.109ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.920s	3.206ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.120s	4.020ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.488m	44.472ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.718m	56.048ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.868m	3.645ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.325m	20.374ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.868m	3.645ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.488m	44.472ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.488m	44.472ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.488m	44.472ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.488m	44.472ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.488m	44.472ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.868m	3.645ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.868m	3.645ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	45.110s	32.851ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	45.110s	32.851ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	45.110s	32.851ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.325m	20.374ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.488m	44.472ms	50	50	100.00
		rom_ctrl_kmac_err_chk	36.390s	39.042ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.488m	44.472ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.488m	44.472ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.488m	44.472ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.718m	56.048ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.868m	3.645ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.383h	40.780ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			467	500	93.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.49	96.97	93.02	97.88	100.00	98.37	98.04	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 22 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.113834909879627757323258912969087557444003781829573189603188850925789676377933
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 485672980 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 485672980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.34687548344605433854351181368715136173961522539387016463440936524054679801113
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7508622000 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7508622000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 9 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.100626188165127061682336125676549544012762466420672201982794102175076885478353
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c21d2e44-f4b8-488e-82f8-37f8a0cbd72d
```
  - 1.rom_ctrl_stress_all_with_rand_reset.112627908415891387280098633724765213150086672427174324907364193944321061359942
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:96ae8dc9-dac0-4573-abf3-086c08ebadb7
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 38.rom_ctrl_stress_all_with_rand_reset.73594851502802707474122536761845608363720179350430203742428719844073465234318
    Line 263, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10992477281 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x5ba02de3
  UVM_INFO @ 10992477281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.rom_ctrl_stress_all_with_rand_reset.37094551098217058737470642979506712281519592427692967602922712953454550536711
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/41.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10016728416 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x2e046cc7
  UVM_INFO @ 10016728416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: b29ffbb03c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `b29ffbb03c`