ROM_CTRL/32KB Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	37.640s	3.680ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.350s	2.116ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.580s	2.136ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	15.390s	3.691ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.250s	2.265ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.920s	1.771ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.580s	2.136ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.250s	2.265ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.000s	3.596ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.590s	1.538ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.270s	4.261ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.708m	15.535ms	49	50	98.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.170s	4.384ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.060s	9.643ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.970s	12.552ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.970s	12.552ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.350s	2.116ms	5	5	100.00
		rom_ctrl_csr_rw	16.580s	2.136ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.250s	2.265ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.580s	5.210ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.350s	2.116ms	5	5	100.00
		rom_ctrl_csr_rw	16.580s	2.136ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.250s	2.265ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.580s	5.210ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.289m	82.128ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.339m	38.084ms	19	20	95.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.030m	1.986ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.313m	8.728ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.030m	1.986ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.289m	82.128ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.289m	82.128ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.289m	82.128ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.289m	82.128ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.289m	82.128ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.030m	1.986ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.030m	1.986ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	37.640s	3.680ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	37.640s	3.680ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	37.640s	3.680ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.313m	8.728ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.289m	82.128ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.170s	4.384ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.289m	82.128ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.289m	82.128ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.289m	82.128ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.339m	38.084ms	19	20	95.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.030m	1.986ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.803h	117.818ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.57	96.97	93.16	97.88	100.00	98.69	97.89	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 27 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.79247715421381700953928714386835791141520914153682347786436652864456950718042
    Line 443, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24982862172 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 24982862172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.77971469876407797891741573953553097539202904589833382800394428687887019519846
    Line 579, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 157722809073 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 157722809073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 25 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 11.rom_ctrl_stress_all_with_rand_reset.91836662740062569996884042028541617409583363911389414516350117777894277867314
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:da3ba26c-4661-4409-91f7-18981d4c089a
```
  - 16.rom_ctrl_stress_all_with_rand_reset.95263704339844629174670529449123923082146518416685302259559514365608646337541
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/16.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:38bb503f-90f2-42fc-af6c-bfa4380b3737
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.20455784833796499107460182489289839115121102047243462530696688899440238991916
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10008287135 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x45d447cf
  UVM_INFO @ 10008287135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.rom_ctrl_stress_all_with_rand_reset.19109544618131526548398729733386158896695911823092995133021171380541079844158
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/40.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10008336077 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xf007f73b
  UVM_INFO @ 10008336077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 13.rom_ctrl_passthru_mem_tl_intg_err.42399900764324244081105519749872206271369599582151456941492878933498990230612
    Line 263, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all has 1 failures.
  - 28.rom_ctrl_stress_all.608108654188350109332443101845454525918726259954898195954647269383103967851
    Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/28.rom_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 40174118330 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x6ae171f0
  UVM_INFO @ 40174118330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8cb25a6867`