ROM_CTRL/32KB Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.190s	10.599ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.180s	1.558ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.370s	8.374ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.850s	2.129ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.310s	15.551ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.450s	7.510ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.370s	8.374ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.310s	15.551ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.620s	1.928ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.070s	2.537ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.650s	8.438ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.589m	65.357ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.380s	38.734ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.840s	22.022ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.890s	2.104ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.890s	2.104ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.180s	1.558ms	5	5	100.00
		rom_ctrl_csr_rw	16.370s	8.374ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.310s	15.551ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.910s	11.132ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.180s	1.558ms	5	5	100.00
		rom_ctrl_csr_rw	16.370s	8.374ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.310s	15.551ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	18.910s	11.132ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.842m	249.901ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.561m	12.322ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.684m	420.878us	5	5	100.00
		rom_ctrl_tl_intg_err	1.299m	2.224ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.684m	420.878us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.842m	249.901ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.842m	249.901ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.842m	249.901ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.842m	249.901ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.842m	249.901ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.684m	420.878us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.684m	420.878us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.190s	10.599ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.190s	10.599ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.190s	10.599ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.299m	2.224ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.842m	249.901ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.380s	38.734ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.842m	249.901ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.842m	249.901ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.842m	249.901ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.561m	12.322ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.684m	420.878us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.639h	40.012ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			472	500	94.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.31	96.88	92.13	97.72	100.00	98.62	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 21 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.15337129926987560649629715542110275669216496090543989160213198378840211851470
    Line 380, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21250994167 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 21250994167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.rom_ctrl_stress_all_with_rand_reset.2996702815253009971238106631856337915425775084805768254171170285728700997810
    Line 341, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10962310705 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10962310705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 6 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.100980144875951678986428953357310696983575936491864323518355881366801281842323
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5a12eb5d-6362-4937-8cc1-1c36c066dea2
```
  - 6.rom_ctrl_stress_all_with_rand_reset.35796777961632784597090968493728276122437080370540634583402543599474053023730
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:33c7e9a6-daf7-49bf-8946-a3261cf4d9db
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.36964468705821934488074070131657925540133688143172356221937865147972509151001
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10007341650 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xd1cfc45e
  UVM_INFO @ 10007341650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `32d52b8d41`