ROM_CTRL/32KB Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: `01a208901a`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	42.560s	3.969ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	16.900s	15.135ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.420s	4.121ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	17.090s	8.734ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.970s	4.011ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.790s	7.687ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.420s	4.121ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.970s	4.011ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.670s	4.473ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.550s	7.552ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.900s	40.294ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.790m	51.145ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.720s	17.857ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	16.630s	2.113ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.420s	8.329ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.420s	8.329ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	16.900s	15.135ms	5	5	100.00
		rom_ctrl_csr_rw	16.420s	4.121ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.970s	4.011ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.550s	8.277ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	16.900s	15.135ms	5	5	100.00
		rom_ctrl_csr_rw	16.420s	4.121ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.970s	4.011ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.550s	8.277ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	7.333m	46.551ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.389m	40.481ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.069m	7.961ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.321m	2.334ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.069m	7.961ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.333m	46.551ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.333m	46.551ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.333m	46.551ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.333m	46.551ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.333m	46.551ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.069m	7.961ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.069m	7.961ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	42.560s	3.969ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	42.560s	3.969ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	42.560s	3.969ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.321m	2.334ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	7.333m	46.551ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.720s	17.857ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	7.333m	46.551ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	7.333m	46.551ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	7.333m	46.551ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.389m	40.481ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.069m	7.961ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.811h	62.720ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			466	500	93.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.55	96.97	93.02	97.88	100.00	98.69	97.89	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 25 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.109410244153752851093095885746370761598542000844289664730287867925916656402532
    Line 266, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11664916547 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11664916547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.63863012241193940179999015366745356080260698310298132881242622303716157367491
    Line 326, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14120790446 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14120790446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 8 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.100413024918643210117492987345122092397833715352431061989054553934722851731001
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3734dd09-cebe-4944-9c78-f6228dc7e2c1
```
  - 9.rom_ctrl_stress_all_with_rand_reset.102373548508045833412087092150195646610849553829240257704527727885162951177724
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8326af17-2f36-46e4-a0bf-708e4f18b238
```
  - ... and 6 more failures.
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 1 failures.
  - 45.rom_ctrl_stress_all_with_rand_reset.12966887550235481937494530037368071949743222258616224389466366289851432021003
    Line 442, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/45.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 304760541106 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 304760541106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `01a208901a`