ROM_CTRL/32KB Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: `a8c9c17a8c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	41.390s	70.701ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.790s	5.590ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	17.510s	2.098ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	17.080s	18.731ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.940s	7.732ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.460s	7.204ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	17.510s	2.098ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.940s	7.732ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	18.080s	8.860ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	15.080s	23.884ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.910s	4.177ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.371m	35.775ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.050s	17.120ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.150s	2.148ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	18.980s	3.509ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	18.980s	3.509ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.790s	5.590ms	5	5	100.00
		rom_ctrl_csr_rw	17.510s	2.098ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.940s	7.732ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.370s	2.005ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.790s	5.590ms	5	5	100.00
		rom_ctrl_csr_rw	17.510s	2.098ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.940s	7.732ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.370s	2.005ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.812m	373.422ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.480m	21.120ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.841m	8.433ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.452m	1.727ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.841m	8.433ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.812m	373.422ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.812m	373.422ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.812m	373.422ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.812m	373.422ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.812m	373.422ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.841m	8.433ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.841m	8.433ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	41.390s	70.701ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	41.390s	70.701ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	41.390s	70.701ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.452m	1.727ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.812m	373.422ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.050s	17.120ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.812m	373.422ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.812m	373.422ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.812m	373.422ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.480m	21.120ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.841m	8.433ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.480h	32.239ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			468	500	93.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.34	96.89	91.99	97.72	100.00	98.28	97.45	99.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 25 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.76458864898571004166851087871495454941160816715385903744814169551995954039479
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 123040371 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 123040371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.rom_ctrl_stress_all_with_rand_reset.103374397263962834002571082410187302335503451408320266033412013775857843758480
    Line 414, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112459848465 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112459848465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.61396776159881486948010383050137089742511032823439420099960988359204021707792
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:4e8659dc-52a8-4de0-af18-4b50ad9ce5b3
```
  - 12.rom_ctrl_stress_all_with_rand_reset.73936466829226973249981477889548638226643318218086789840869300314512108883185
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5ccc6c3e-fae5-4e85-9305-c6a21c8c07c3
```
  - ... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 3 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.29149593329682212453334760328089392569347757172651608200434169910990703844854
    Line 316, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 140258855341 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x98a2953a
  UVM_INFO @ 140258855341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.rom_ctrl_stress_all_with_rand_reset.114196090402208449659460932011910801358179202106346460253982453335137692187499
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10024344351 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xdd287bbb
  UVM_INFO @ 10024344351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

ROM_CTRL/32KB Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `a8c9c17a8c`