ROM_CTRL/32KB Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: `dd5ad5fb77`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	42.870s	8.362ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.380s	2.120ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.730s	2.047ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.620s	11.383ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.470s	1.814ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.720s	7.475ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.730s	2.047ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.470s	1.814ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.090s	1.938ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	12.710s	7.191ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.650s	4.463ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.921m	47.177ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.470s	4.384ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.020s	2.139ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	20.580s	2.210ms	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	20.580s	2.210ms	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.380s	2.120ms	5	5	100.00
		rom_ctrl_csr_rw	16.730s	2.047ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.470s	1.814ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.490s	3.859ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.380s	2.120ms	5	5	100.00
		rom_ctrl_csr_rw	16.730s	2.047ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.470s	1.814ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.490s	3.859ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.627m	240.309ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.659m	13.335ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.655m	1.188ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.297m	1.960ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.655m	1.188ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.627m	240.309ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.627m	240.309ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.627m	240.309ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.627m	240.309ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.627m	240.309ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.655m	1.188ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.655m	1.188ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	42.870s	8.362ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	42.870s	8.362ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	42.870s	8.362ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.297m	1.960ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.627m	240.309ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.470s	4.384ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.627m	240.309ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.627m	240.309ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.627m	240.309ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.659m	13.335ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.655m	1.188ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.854h	30.948ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			462	500	92.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.42	96.89	92.56	97.72	100.00	98.97	97.45	98.37

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 30 failures.
  - 0.rom_ctrl_stress_all_with_rand_reset.97981439815836869941104337668408778652453322916894847478100354919171842409421
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 429521388 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 429521388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rom_ctrl_stress_all_with_rand_reset.22772659191524469203397634508087198594304450365846535368086017110921478516535
    Line 528, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30948196081 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30948196081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 5 failures.
  - 2.rom_ctrl_stress_all_with_rand_reset.59435813545401425949893069742869423627773657039998504571544831772538729163217
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:36354aea-fcbf-442b-87f3-06ad188a2786
```
  - 15.rom_ctrl_stress_all_with_rand_reset.9702369520169651336330571249286472079167018860472438508327856748745936841322
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:5b093f18-6c9a-4ca4-a600-a4c42a28722d
```
  - ... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 2 failures.
  - 27.rom_ctrl_stress_all_with_rand_reset.100987637442765890430618275535202631076640061013141257715716238955891304055917
    Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/27.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11095669809 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x79361c48
  UVM_INFO @ 11095669809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.rom_ctrl_stress_all_with_rand_reset.39818701884142272130154216589484952036055286075757096261646106721109327569148
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/38.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10014250603 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xca2fd971
  UVM_INFO @ 10014250603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_tl_errors has 1 failures.
  - 11.rom_ctrl_tl_errors.85922986294273098446423268905926915406238630893176588065477236903416556775250
    Line 252, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 1654434651 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1654434651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

ROM_CTRL/32KB Simulation Results

Tuesday June 11 2024 19:02:38 UTC

GitHub Revision: dd5ad5fb77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 66418170746903624595625818392428707033482455256751560525176982524210226376736

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `dd5ad5fb77`