ROM_CTRL/32KB Simulation Results

Thursday June 13 2024 19:02:12 UTC

GitHub Revision: 548a3880d8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 95435389850697596633112362018639443702533575559488568730544091582583938649085

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	43.060s	8.258ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	17.080s	3.852ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	16.240s	4.316ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	16.800s	8.177ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	16.060s	2.052ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	17.440s	26.157ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	16.240s	4.316ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.060s	2.052ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	16.700s	24.717ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.900s	1.189ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	18.190s	8.242ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.573m	21.065ms	48	50	96.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	34.360s	5.508ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.910s	11.822ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	21.200s	4.005ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	21.200s	4.005ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	17.080s	3.852ms	5	5	100.00
		rom_ctrl_csr_rw	16.240s	4.316ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.060s	2.052ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.170s	2.089ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	17.080s	3.852ms	5	5	100.00
		rom_ctrl_csr_rw	16.240s	4.316ms	20	20	100.00
		rom_ctrl_csr_aliasing	16.060s	2.052ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	16.170s	2.089ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	8.749m	109.390ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.372m	39.452ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.831m	4.178ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.300m	3.718ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.831m	4.178ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.749m	109.390ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.749m	109.390ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.749m	109.390ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.749m	109.390ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.749m	109.390ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.831m	4.178ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.831m	4.178ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	43.060s	8.258ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	43.060s	8.258ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	43.060s	8.258ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.300m	3.718ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	8.749m	109.390ms	50	50	100.00
		rom_ctrl_kmac_err_chk	34.360s	5.508ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	8.749m	109.390ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	8.749m	109.390ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	8.749m	109.390ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.372m	39.452ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.831m	4.178ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.052h	38.104ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			461	500	92.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	96.89	91.99	97.72	100.00	98.62	97.45	98.37

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 26 failures.

    • 1.rom_ctrl_stress_all_with_rand_reset.2505882227945704690401940133566611105208402983762231489145715625191937379556
      Line 303, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6021879371 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6021879371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.rom_ctrl_stress_all_with_rand_reset.80607019409912109659337695894278867633407980946269902397067223683246473018225
      Line 256, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3968752905 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3968752905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

• Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 10 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 10 failures.

    • 3.rom_ctrl_stress_all_with_rand_reset.81277516597821318802719601163334965334633773901391356057940553976541518322503
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:407bc061-8689-42f5-b21a-65df57ae32c6
      

    • 11.rom_ctrl_stress_all_with_rand_reset.87113547391007282972876563021453057323446067405750440810903702563600805692657
      Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/11.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:a765cef2-8476-4819-b3cd-54fda1193491
      

    • ... and 8 more failures.

• UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 2 failures:

  • Test rom_ctrl_stress_all has 2 failures.

    • 8.rom_ctrl_stress_all.112471337541251071855343787376592534234015412166744303355400529159897608980500
      Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 3572565624 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 3572565624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 23.rom_ctrl_stress_all.87266282297916141489675404569125888135761275860204744611043819204891158969163
      Line 255, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/23.rom_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 7416452792 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
        UVM_INFO @ 7416452792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.rom_ctrl_stress_all_with_rand_reset.24314567597589805061427703555856029255331225465784661436709350688623277069769
      Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/30.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10020962277 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x3cb6b8b2
        UVM_INFO @ 10020962277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.06.12_04.56.54
• 2024.06.11_11.58.44
• 2024.06.10_06.47.33
• 2024.06.08_13.11.50
• 2024.06.07_04.55.31
• 2024.06.06_11.05.59
• 2024.06.05_03.59.29