ROM_CTRL/32KB Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: `25e609d6bb`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	43.780s	8.554ms	50	50	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	18.300s	34.321ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	15.590s	7.142ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.880s	11.642ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	15.340s	8.364ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	16.450s	14.954ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	15.590s	7.142ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.340s	8.364ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	14.440s	1.906ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	14.990s	7.988ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	17.600s	8.907ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.428m	15.647ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	35.230s	4.440ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	17.210s	2.190ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	19.840s	3.908ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	19.840s	3.908ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	18.300s	34.321ms	5	5	100.00
		rom_ctrl_csr_rw	15.590s	7.142ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.340s	8.364ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.560s	5.932ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	18.300s	34.321ms	5	5	100.00
		rom_ctrl_csr_rw	15.590s	7.142ms	20	20	100.00
		rom_ctrl_csr_aliasing	15.340s	8.364ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.560s	5.932ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	9.598m	342.936ms	50	50	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.725m	18.076ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.874m	1.380ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.288m	3.536ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.874m	1.380ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.598m	342.936ms	50	50	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.598m	342.936ms	50	50	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.598m	342.936ms	50	50	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.598m	342.936ms	50	50	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.598m	342.936ms	50	50	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.874m	1.380ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.874m	1.380ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	43.780s	8.554ms	50	50	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	43.780s	8.554ms	50	50	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	43.780s	8.554ms	50	50	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.288m	3.536ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	9.598m	342.936ms	50	50	100.00
		rom_ctrl_kmac_err_chk	35.230s	4.440ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	9.598m	342.936ms	50	50	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	9.598m	342.936ms	50	50	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	9.598m	342.936ms	50	50	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.725m	18.076ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.874m	1.380ms	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.833h	31.469ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			464	500	92.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.38	96.89	92.42	97.67	100.00	98.62	97.45	98.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 25 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.78507170114769213619590723553706620732006114603819127995892580321513943151268
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2437368046 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2437368046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_ctrl_stress_all_with_rand_reset.69198960834490751838146153038838099969860327441108335072277047687375781076630
    Line 440, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 82713950684 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 82713950684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
Job rom_ctrl_32kB-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 7 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.64389116621324057076204758986140488409389299301446935114955452831753167284691
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:85a5c1fc-619a-49b9-94ca-584d0714dec3
```
  - 13.rom_ctrl_stress_all_with_rand_reset.113121374356765216273052116210683745573630580512824675989858607551738754478907
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/13.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:028af8ad-8e67-401e-a994-06bb5647e0f3
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:250) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 4 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 4 failures.
  - 8.rom_ctrl_stress_all_with_rand_reset.1570367018949256981742350914519251615793689249742395441487828135988839919154
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/8.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10023498602 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xdaf5a947
  UVM_INFO @ 10023498602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.rom_ctrl_stress_all_with_rand_reset.67247021784657847897914997858377043994025840563430573071659347822204121053474
    Line 254, in log /container/opentitan-public/scratch/os_regression/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10012791449 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0xc8fc4bee
  UVM_INFO @ 10012791449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

ROM_CTRL/32KB Simulation Results

Sunday June 23 2024 23:02:35 UTC

GitHub Revision: 25e609d6bb

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 43520053114197278442322840927374150239284669988213580416404649115121474470865

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `25e609d6bb`